Simulation Results

Simulation Results: rv_dm/use_dmi_interface

18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
91.78 %

code
82.64 %

assert
96.90 %

func
95.79 %

block
93.18 %

line
93.82 %

branch
81.50 %

toggle
74.89 %

FSM
80.36 %

Validation stages

V1		93.08%
V2		37.78%
V2S		96.00%
V3		0.00%
unmapped		0.00%

121/130 passed

93.08 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	54.000s	1598.921us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	47.000s	125.042us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	52.000s	406.557us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	63.000s	35971.268us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	52.000s	413.764us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	53.000s	3804.105us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	78.000s	14679.730us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	176.000s	73170.401us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	56.000s	9533.701us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	50.000s	266.273us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	52.000s	427.976us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	43.000s	465.839us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	47.000s	79.595us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	53.000s	150.951us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	50.000s	783.873us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	50.000s	91.411us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	55.000s	372.094us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	50.000s	266.273us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	50.000s	313.675us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	54.000s	887.480us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	43.000s	465.839us	2	2	100.00
rom_read_access				0	2	0.00
	rv_dm_rom_read_access	49.000s	117.319us	0	2	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	44.000s	742.214us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	47.000s	450.268us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	55.000s	4300.237us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	45.000s	2314.773us	1	1	100.00
csr_mem_rw_with_rand_reset				0	5	0.00
	rv_dm_csr_mem_rw_with_rand_reset	49.000s	36.046us	0	5	0.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	45.000s	2314.773us	1	1	100.00
	rv_dm_csr_rw	47.000s	450.268us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	40.000s	78.326us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	52.000s	35.353us	1	1	100.00

68/180 passed

37.78 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	54.000s	1598.921us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	52.000s	604.314us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	47.000s	412.442us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	52.000s	308.312us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	52.000s	619.545us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	82.000s	13692.988us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	51.000s	266.656us	0	20	0.00
bad_sba				3	20	15.00
	rv_dm_bad_sba_tl_access	71.000s	9618.189us	3	20	15.00
sba_autoincrement				2	20	10.00
	rv_dm_autoincr_sba_tl_access	118.000s	51479.561us	2	20	10.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	49.000s	142.671us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	45.000s	1425.435us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	52.000s	878.518us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	52.000s	57.861us	0	5	0.00
tap_ctrl_transitions				0	11	0.00
	rv_dm_tap_fsm	52.000s	20.797us	0	1	0.00
	rv_dm_tap_fsm_rand_reset	51.000s	131.373us	0	10	0.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	37.000s	96.584us	1	1	100.00
stress_all				1	20	5.00
	rv_dm_stress_all	10800.000s	0.000us	1	20	5.00
alert_test				10	10	100.00
	rv_dm_alert_test	51.000s	66.113us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	56.000s	165.388us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	56.000s	165.388us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	45.000s	2314.773us	1	1	100.00
	rv_dm_csr_hw_reset	44.000s	742.214us	1	1	100.00
	rv_dm_csr_rw	47.000s	450.268us	5	5	100.00
	rv_dm_same_csr_outstanding	56.000s	700.855us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	45.000s	2314.773us	1	1	100.00
	rv_dm_csr_hw_reset	44.000s	742.214us	1	1	100.00
	rv_dm_csr_rw	47.000s	450.268us	5	5	100.00
	rv_dm_same_csr_outstanding	56.000s	700.855us	5	5	100.00

V2S

48/50 passed

96.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				28	30	93.33
	rv_dm_sec_cm	51.000s	492.189us	5	5	100.00
	rv_dm_tl_intg_err	64.000s	3812.412us	23	25	92.00
sec_cm_bus_integrity				23	25	92.00
	rv_dm_tl_intg_err	64.000s	3812.412us	23	25	92.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	45.000s	1425.435us	2	2	100.00
	rv_dm_debug_disabled	46.000s	133.604us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	45.000s	1425.435us	2	2	100.00
	rv_dm_debug_disabled	46.000s	133.604us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	54.000s	1598.921us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				10	10	100.00
	rv_dm_buffered_enable	53.000s	239.355us	10	10	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	53.000s	85.267us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	53.000s	85.267us	4	4	100.00
sec_cm_exec_ctrl_mubi				10	10	100.00
	rv_dm_buffered_enable	53.000s	239.355us	10	10	100.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	20	0.00
	rv_dm_stress_all_with_rand_reset	53.000s	20.216us	0	20	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	49.000s	0.591us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:487) [scoreboard] sba_tl_access_q item uncompared:				38 test runs
	rv_dm_sba_tl_access	81873553348653426246780144965163885482570886773343080677073670312308069548055	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24587
	rv_dm_bad_sba_tl_access	45534878834634925466494656075532375633569362089934961922674973403755064984526	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24709
	rv_dm_autoincr_sba_tl_access	30308291726779756451021014054178720784288505720825455448198059495914410033593	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24774
	rv_dm_sba_tl_access	80779604507471266318076749436097307250857563371911974007678910677404602940659	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24588
	rv_dm_autoincr_sba_tl_access	75171163143191947178466788154367019177113099317656252547273959503789852261309	165	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24753
	rv_dm_sba_tl_access	115690733783672108318037065639137756897817806914125465898184111822090105420889	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24606
	rv_dm_bad_sba_tl_access	78576075873977437152013355082486062162983004606135553150673598599007040332988	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24659
	rv_dm_sba_tl_access	55342651730714386910928182310481186358516750683656183725836327990419331162619	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24589
	rv_dm_sba_tl_access	52270343702265986541033501752744540972733938247649779256776694394520527805747	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24585
	rv_dm_bad_sba_tl_access	38802040731202892865443846104225481160952718963415668942768639223696808097375	120	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24676
	rv_dm_autoincr_sba_tl_access	33361731491589343997423649402883784699961847601162919894205219553701422584557	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24559
	rv_dm_sba_tl_access	97241710780803094242498966370165629490956006374218968338228599389412825548612	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24587
	rv_dm_sba_tl_access	7145526769296812875032484206538356305241544118855186636743090236721061404093	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24610
	rv_dm_autoincr_sba_tl_access	84686885040095674681435104971181190410645305877522382305821117404129098836074	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24559
	rv_dm_sba_tl_access	46031762711491280923197540151437919487051635777235020462656994863403165065765	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24589
	rv_dm_bad_sba_tl_access	86670173289613846954559836187011382216840516067329623556026087708130534865754	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24693
	rv_dm_sba_tl_access	26509018139340873820580118140926693931047120685570189953050465688005064995083	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24601
	rv_dm_sba_tl_access	30661659595802871816114572116140674144114257476860927811686029456234074934750	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24659
	rv_dm_bad_sba_tl_access	13843426064442255542889137820462796052108079917252403971465969941454618983294	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24678
	rv_dm_autoincr_sba_tl_access	24342825795659435352132973152480907103410419927300029205412326461223174940397	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24705
	rv_dm_sba_tl_access	79393350712749290817424111611103767038501523092480797243159033961768521056802	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24653
	rv_dm_autoincr_sba_tl_access	47406706098394832440303816218239135333752553091710854012428859318967282356780	147	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24649
	rv_dm_sba_tl_access	50508473718852679730334920517929005212058526681242723795107394991872018751129	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24589
	rv_dm_autoincr_sba_tl_access	111097986947188895239857273652948843197768281202269341251041740825244501141867	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24882
	rv_dm_sba_tl_access	18157850826796509389536636894391466590512796976063521961756833941902820958333	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24609
	rv_dm_bad_sba_tl_access	78373538380290094915057738998344307948507462464705781210052659314049501089451	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24698
	rv_dm_autoincr_sba_tl_access	26745525447798662777210286391653269954545307368303181848636698067640046419984	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24648
	rv_dm_sba_tl_access	51031076110580058181923939353404169720974111013084470082355694542090226758989	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24566
	rv_dm_sba_tl_access	85761061041221201941175584419787150627549467534802016095348814490104881570710	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24651
	rv_dm_bad_sba_tl_access	8716448942485677731854768427070071850457765067135252135335260649111932416241	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10338
	rv_dm_sba_tl_access	28160098809837452521631247183668519933396580359843307978652046063839800375261	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24653
	rv_dm_bad_sba_tl_access	63606021106811688949580839007876093903266756588869189854393163044291076082037	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24537
	rv_dm_sba_tl_access	102594759679786054610464395406494257523808353757577486673562718848014220763078	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24594
	rv_dm_sba_tl_access	57845741735954076339721170704601381349922226810123779846425207264776504341585	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24647
	rv_dm_autoincr_sba_tl_access	101741255934999900578495914764355597123515658084822143181614790274009164343687	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24589
	rv_dm_sba_tl_access	11697547556523107857870018858233049208306618231161163903650673833731743653183	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24650
	rv_dm_bad_sba_tl_access	63747658227397491734103734854323027641720715587911055692410384710876654082244	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24647
	rv_dm_sba_tl_access	29792495543004140090389482808429954205838940360312979215414432037138532799938	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24653
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				37 test runs
	rv_dm_delayed_resp_sba_tl_access	74706200448536281904532272235012279600747446909809115544995333286843626821289	107	UVM_INFO @ 51244711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	19095483017444099533322760772583852134693418245314617102446140054629924863483	107	UVM_INFO @ 362588334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	80414334981869905034166649073804453717655642133788823936130675937251591822569	107	UVM_INFO @ 235674909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	114869182268591266472901971885899279066414054796197676359362850309743842574938	107	UVM_INFO @ 169125853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	69521863736535175692896399755359988865483021605263052188342362410209351901812	107	UVM_INFO @ 50799670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	92183106456128688983702849242400469399025569426485122775608719634134467538973	107	UVM_INFO @ 191251669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	19841795481537868118141694718281226304955246112363201184248654346293319323356	107	UVM_INFO @ 174701763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	109358911401353709084682410646029993111731397127706503151530043355923432625122	107	UVM_INFO @ 153842377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	18437685447405987887458966127236380242909255751931752459462697101919559344724	107	UVM_INFO @ 126001340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	80296579585352042550448706044157294438181799183016655326992704077064336923383	107	UVM_INFO @ 1859811591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	31723313066490504761485846716897787925527809027088833813612079540315712175662	107	UVM_INFO @ 293202847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	31831823013764435244456475515112136600693311183637859257791335573227623663842	107	UVM_INFO @ 408549188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	81956344918949081635787824312323676975296774363826339313910846261781723803195	107	UVM_INFO @ 190016982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	65640202900594401485853357898938369321865443155209216846505263890858722348798	107	UVM_INFO @ 75395517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	15394134672587676002638548593460684634452204226441295901359637817674081310588	107	UVM_INFO @ 240628731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	50402763128645987296668863426558201284716943350847099908992188982997067537585	107	UVM_INFO @ 231090105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	97559676901014462433453507861960942771989024207215809786267029772517641299609	107	UVM_INFO @ 195132493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	40215442770254087535666941398223055557658285229453533815033515000760257490293	107	UVM_INFO @ 87549989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	111944752997349557880508270207647191426530588553193274856730075136974724193802	107	UVM_INFO @ 92032916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	44180291789041687954931720955983768596720516976979640645824180885621749395515	107	UVM_INFO @ 56394947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	7565474726394746607533766932843461174088081863108367601874281884498819832286	107	UVM_INFO @ 101129586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	70468342853705551841965912854131293485170426132096042107037443090100080777267	107	UVM_INFO @ 652227831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	70681554078392978416926483045713754137912286178671297159673035662810211362066	107	UVM_INFO @ 130891135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	40809934640894977350530478615773060489092847875016296801411524182961127716730	107	UVM_INFO @ 489366154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	42768087044182382726757004427633833073864533308715425540382182987810153017396	107	UVM_INFO @ 23004738551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	83482229889430586530991710589143907075878708253636171183675291511470473224545	107	UVM_INFO @ 227262969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	65990602648405852788958348850227645693449427507394759659649970652658891827863	107	UVM_INFO @ 124574156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	82905011106690883278798168269918280733834164110715279961020332489796677031222	107	UVM_INFO @ 172265587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	36950429818156304621721603107357706928371561092197472564459972921277331564704	107	UVM_INFO @ 66042367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	11829873170449851217456182410426923544967695099078489756231775753903104370646	107	UVM_INFO @ 761257348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	2700443497673953073507582283535321821407088954967676667950041963092170187266	137	UVM_INFO @ 21687518382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	2533638375209961196337614540850884800980877751382125142429846468349569086332	107	UVM_INFO @ 332460439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	95744756582702977990682243683077231876620231652598856559263058088867395911323	107	UVM_INFO @ 286430149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	91443692416674886945578483113892318255171787759959994982690294185966194186456	107	UVM_INFO @ 185562786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	114251986961934120340647591364401470097545713641025531681819079460405188573888	107	UVM_INFO @ 441959351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	74285684994958632328526254387374465256457750041495343538651996755482112943224	107	UVM_INFO @ 266656133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	108879830687687269503911749014688187029055101811826755795181931699109866911402	107	UVM_INFO @ 314004562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_stress_all_vseq] m_mode_sequencer not configured.				20 test runs
	rv_dm_stress_all_with_rand_reset	46528507256964463294749594620407404123549810364609773541645324419666478860086	90	UVM_INFO @ 22467989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	7223420505843177137677236163158739044307094419657502217210578975206349844624	90	UVM_INFO @ 83695135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	11988903482578608927094134287077935753812374650577277503536637319975920636691	90	UVM_INFO @ 54503348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	94051375305295290337581123260239712715059998056145021332122877221990109521171	90	UVM_INFO @ 111542810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	19318466918979331292091342599464870706385715037755710059044891548734021496258	90	UVM_INFO @ 19403497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	7247787892889688405570370974317081526082730075369312769730958649199291153997	90	UVM_INFO @ 55280506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	40186276878595957576219814222446738460553440417029331826054635936095072467692	90	UVM_INFO @ 37148613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	91319339463020401094106214719425208459670226292771012152201061730487568406565	90	UVM_INFO @ 38358131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	63370003795587252859547161999141965562742692825099736589217885043744962606740	90	UVM_INFO @ 92833256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	81085483497054363985216566830610988355006529179886051644196614332279124687797	90	UVM_INFO @ 107528539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	84305853725631434206659252627435375498226980554152324848684543357499753643395	90	UVM_INFO @ 21039586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	66724885719335334883104014390418135815453408683432126619472750128655036864430	90	UVM_INFO @ 108992044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	107341425199014828325488046965185444165220110434037135668426927855421646287143	90	UVM_INFO @ 43049055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	69180734212009849232838358797175607896596611475108553273109830745981356465257	90	UVM_INFO @ 68229418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	75252319296441437138644507960113025359432149649230008095432906807620180381373	90	UVM_INFO @ 37485483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	56429248852976663519225512240771512954653691735722416370231486887944508243100	90	UVM_INFO @ 20215721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	32791597129578095667597034556130929501836770013015102480644049179570816121606	90	UVM_INFO @ 153001463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	1151490002124997670468202724078120598364838869046243654803372213006801513654	90	UVM_INFO @ 65770363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	92900433138415327955892491685753836580735790251547010322520599429225757369828	90	UVM_INFO @ 77076497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	3678370006946106348327487088285277205567252075369340331022301690579132275631	90	UVM_INFO @ 19224570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				11 test runs
	rv_dm_hart_unavail	37069744511550225898088561576308224409760953724177697796420314497203871857472	87	UVM_INFO @ 104522356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	86246440098984049366514057736432523920571970276719626777705615202433142425726	87	UVM_INFO @ 57861128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	22330496526540438746830602532112218906196129878257329140679296957642634895889	87	UVM_INFO @ 78075608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	4517599564056987306437227967024093997453624319976095415293033468886280235122	87	UVM_INFO @ 220627183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	11305110451391611544380353715081126772128201179818872405198568228000274181818	90	UVM_INFO @ 1405789015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	6213858934074148154990915517073117607026120764154820224398208285000672711047	87	UVM_INFO @ 108673659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	20387202068634280276156697007679691419421127268114618294559439611758654038478	93	UVM_INFO @ 5180764255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	113780248072595787095730038124713504530846350494530638706398385149428398737687	88	UVM_INFO @ 458943233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	54447038721413568189146419547307528529541641606525414794628062432832803682163	89	UVM_INFO @ 1035361515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72984784930746699486831456240602609599707035607328671779329952467243531234520	94	UVM_INFO @ 3637677115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	15162456645135256521674818152684144771539057644290722911118167611906825477639	89	UVM_INFO @ 1314754841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_tap_fsm_vseq] m_mode_sequencer not configured.				10 test runs
	rv_dm_tap_fsm_rand_reset	35565337412236783520647396958885522859424067968976518687880404016071353395667	90	UVM_INFO @ 20773813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tap_fsm_rand_reset	5930951408045589723138374413626643943620668166741084894641300574898956066322	90	UVM_INFO @ 25366202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tap_fsm_rand_reset	113542733432016737680134995732472692124897158688903405770421859005450293206226	90	UVM_INFO @ 120638694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tap_fsm_rand_reset	60667820226768449373363354782717990729024620736884005273606743817350292823805	90	UVM_INFO @ 24110845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tap_fsm_rand_reset	106057635108114955233108745285740579505963558245249235065810807742644221534561	90	UVM_INFO @ 131373199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tap_fsm_rand_reset	63086929181358944207660054183132934134568223834136882412514551039982230410245	90	UVM_INFO @ 65461580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tap_fsm_rand_reset	57738209840220104941408507030734048406811616489102350782396282638119838568128	90	UVM_INFO @ 80640650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tap_fsm_rand_reset	73056664564957482156573948642012705916023131233381464614462152906267065671813	90	UVM_INFO @ 19183871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tap_fsm_rand_reset	13317161030752069550381714462778653274531153474377382760930787707207924414521	90	UVM_INFO @ 31261317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tap_fsm_rand_reset	101354616772969298813216069345271290634142096104561880131795459358697733808693	90	UVM_INFO @ 69330774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				8 test runs
	rv_dm_jtag_dmi_debug_disabled	32691382511916734180026751853109509797823664540395242795364190567006248927858	87	UVM_INFO @ 218344349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	18768888745731943745048044940749220120330093858569617911098143555615181709620	92	UVM_INFO @ 1484537536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	46380266341804168888495872208902008468249330803195617261653725497650382343411	87	UVM_INFO @ 142670840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	48934121596231915699856122143225291518104571288408271652174067047723007709331	102	UVM_INFO @ 4581345207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	93757462400997418176968699756807729103501019192707837420108540793600183765927	89	UVM_INFO @ 790654342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	65797263619993050161187387562224013793450678365211298743399807365154094455992	88	UVM_INFO @ 227189309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	65909093589040271484416420580720841530168941673379130301987160248027673725575	91	UVM_INFO @ 1207785217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	34338742364890135225905456739502652041618534456650722687109728395981032265525	91	UVM_INFO @ 3139553180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				5 test runs
	rv_dm_mem_tl_access_resuming	19084595032514125989395042413553780111408542471990067375040954499931299927506	87	UVM_INFO @ 79594905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	3801781104895538460961899549088689500325684461155218431033637029643275707011	87	UVM_INFO @ 98196172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	8259681175168751254420092784782907319383067197007035531201101088430791499285	91	UVM_INFO @ 1207932131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	45068089199125333854380082648951690560994278662169714406506441283703269043850	93	UVM_INFO @ 1456715960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	81664340560262108379458561756977984125654951749901718475872663635615127946385	89	UVM_INFO @ 407678200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_common_vseq] m_mode_sequencer not configured.				5 test runs
	rv_dm_csr_mem_rw_with_rand_reset	111146135264506690863219589202087507546460084898012455474672984852280396554449	90	UVM_INFO @ 21924179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_csr_mem_rw_with_rand_reset	3769731456209237320675555576636077118300905201564231207174533211161523349558	90	UVM_INFO @ 96620772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_csr_mem_rw_with_rand_reset	114033039332649001892715018601157627404814269950839024331734846299525802349352	90	UVM_INFO @ 36046277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_csr_mem_rw_with_rand_reset	69487297007386058433619022887647685800203081011456223097770145782259504229233	90	UVM_INFO @ 34268941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_csr_mem_rw_with_rand_reset	30372285128642602931549911298750873295846266540982105537234441115162872834903	90	UVM_INFO @ 37761509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	rv_dm_stress_all	14983978926411316360780758100731316103407885314363165540890549659140219727449	None
	rv_dm_stress_all	37490384095428349971996161858637940797963618769235112278002396646643975446818	None
	rv_dm_stress_all	12061965166780052077406363804149654292905346101877337460685303149221720757429	None
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [rv_dm_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				2 test runs
	rv_dm_tl_intg_err	91463647645866451882907825213237755605141412038531493376899381754521673127147	161	UVM_INFO @ 723505141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tl_intg_err	38946605114598858915413514892619978885191007543243859182246733789814371726715	120	UVM_INFO @ 841194871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [seq] m_mode_sequencer not configured.				1 test run
	rv_dm_tap_fsm	78303896907046958213184923614235225213096740224576775112366461438274106249585	88	UVM_INFO @ 20797370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:415) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@24641) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	69465208110511997691103874735599037349502225747193036951611463734988840600621	87	). UVM_INFO @ 117318678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_/rtl/tlul_assert.sv,381): Assertion aKnown_AKnownEnable has failed				1 test run
	rv_dm_scanmode	73700931401424366691827859674586035381289654624724438524768316616844881553567	87	UVM_ERROR @ 590946 ps: (tlul_assert.sv:381) [ASSERT FAILED] aKnown_AKnownEnable UVM_INFO @ 590946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:415) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@24645) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	109858041607764955757417795020588608528345595513299689791263199185058998954906	87	). UVM_INFO @ 119673669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_stress_all	28133501164071776259506154063228299368247301083443749415962003742848440452016	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---