Simulation Results: rv_timer

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.29 %
  • code
  • 90.45 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 567.691us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 2.000s 40.799us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 2.000s 13.106us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 304.802us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 35.948us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 143.702us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 2.000s 13.106us 5 5 100.00
rv_timer_csr_aliasing 1.000s 35.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 20 20 100.00
rv_timer_random_reset 7.000s 14498.305us 20 20 100.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 3066.501us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 383.000s 764746.487us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 383.000s 764746.487us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 7.000s 4915.666us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 1.000s 46.637us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 1.000s 25.457us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 97.975us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 97.975us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 2.000s 40.799us 1 1 100.00
rv_timer_csr_rw 2.000s 13.106us 5 5 100.00
rv_timer_csr_aliasing 1.000s 35.948us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 38.613us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 2.000s 40.799us 1 1 100.00
rv_timer_csr_rw 2.000s 13.106us 5 5 100.00
rv_timer_csr_aliasing 1.000s 35.948us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 38.613us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 2.000s 386.989us 5 5 100.00
rv_timer_tl_intg_err 2.000s 285.841us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 285.841us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 3 10 30.00
rv_timer_min 3.000s 919.753us 3 10 30.00
max_value 1 10 10.00
rv_timer_max 2.000s 936.882us 1 10 10.00
stress_all_with_rand_reset 20 20 100.00
rv_timer_stress_all_with_rand_reset 59.000s 21735.762us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 8 test runs
rv_timer_max 99248540003318297072869392814915781989187687427849827038265990241431282924521 84
UVM_INFO @ 91850621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 2482238794053344582796078461507778980759875970508044611496373855572512028813 84
UVM_INFO @ 173994963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 93751249413732051049423041931417506432492564937737068855253234578797477934868 85
UVM_INFO @ 48127847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 24697895591737338248004649301824788482662877422005905246312358543527512468228 85
UVM_INFO @ 53660011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 29972558258567645131117289178159822977493618376311268238620752091169863107504 84
UVM_INFO @ 88334844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 6208288705205275065975147026228856154627100521383267093493877695938578782918 84
UVM_INFO @ 339228891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 68541789869559282247256915384458975620064600729264709864188420910234606820892 84
UVM_INFO @ 178450968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 93520368635766336807783445068611160484543942124038684433910851815913125524737 84
UVM_INFO @ 936882240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 7 test runs
rv_timer_min 111677127168893594961686330903171716039042573415799292377225523393219564302289 86
UVM_INFO @ 280126768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 927918470906101782094170614005611068993666055789102253472088821313173986042 85
UVM_INFO @ 258249680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 3085371852166046288019252753466044349221953393895493465748136124003256497071 84
UVM_INFO @ 919752945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 45681381926111143568560132397022146574211859751040551969782720707515105082884 84
UVM_INFO @ 130171345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 39116173699763512354389113733873614177175022259436668787541015361454444242710 84
UVM_INFO @ 62129779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 14291701222927647947050812345212920772860455446940467607633413864631764747832 84
UVM_INFO @ 262144158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 96291283965280841938146674549405251590451748944480095342845063243249248631279 85
UVM_INFO @ 235161175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:343) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 70779151279663426929592485068795272765508905064381810755040549085291838988406 84
UVM_INFO @ 44364894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---