Simulation Results: spi_host

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.88 %
  • code
  • 91.30 %
  • assert
  • 96.60 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.90%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 72.000s 1933.877us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 50.214us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 16.431us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 82.680us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 16.846us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 66.997us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 16.431us 5 5 100.00
spi_host_csr_aliasing 1.000s 16.846us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 15.574us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 169.170us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 30.159us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 14.000s 572.289us 10 10 100.00
spi_host_error_cmd 2.000s 101.229us 10 10 100.00
spi_host_event 49.000s 6035.989us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 7.000s 1118.567us 10 10 100.00
speed 10 10 100.00
spi_host_speed 7.000s 1118.567us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 7.000s 1118.567us 10 10 100.00
upper_range_clkdiv 4 5 80.00
spi_host_upper_range_clkdiv 977.000s 122130.245us 4 5 80.00
sw_reset 10 10 100.00
spi_host_sw_reset 221.000s 7885.763us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 105.174us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 7.000s 1118.567us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 7.000s 1118.567us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 72.000s 1933.877us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 72.000s 1933.877us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 51.000s 3357.699us 10 10 100.00
spien 10 10 100.00
spi_host_spien 56.000s 3672.313us 10 10 100.00
stall 9 10 90.00
spi_host_status_stall 2146.000s 186746.556us 9 10 90.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 3.000s 187.977us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 14.000s 572.289us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 15.646us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 17.503us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 93.214us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 93.214us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 50.214us 1 1 100.00
spi_host_csr_rw 2.000s 16.431us 5 5 100.00
spi_host_csr_aliasing 1.000s 16.846us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 143.391us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 50.214us 1 1 100.00
spi_host_csr_rw 2.000s 16.431us 5 5 100.00
spi_host_csr_aliasing 1.000s 16.846us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 143.391us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 106.482us 25 25 100.00
spi_host_sec_cm 3.000s 402.514us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 106.482us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 2 test runs
spi_host_status_stall 98934039014746057344751135006957807357720452919297511106214398892198626563084 2128
UVM_INFO @ 68251692637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_upper_range_clkdiv 80483961855136407308030774468084597957858664452081788861142259344406802783925 189
UVM_INFO @ 122130244558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---