| V1 |
|
97.30% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
87.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 85.871us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 20.921us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 14.652us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 3.000s | 58.441us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 1.000s | 54.683us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 4 | 5 | 80.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 7.000s | 10011.037us | 4 | 5 | 80.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 14.652us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 54.683us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 16.000s | 747.767us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 8.000s | 757.849us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 22.000s | 3450.975us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 325.000s | 9880.367us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 13.000s | 3012.781us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 31.000s | 2465.385us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 1744.701us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 18.000s | 3618.069us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 3.000s | 273.541us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 375.000s | 14349.552us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 106.199us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 2.000s | 151.897us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 3.000s | 276.631us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 19.000s | 1024.684us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 151.755us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 85.871us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 3.000s | 273.541us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 31.000s | 2465.385us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 71.000s | 8971.614us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 58.732us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 7.000s | 616.413us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 7.000s | 616.413us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 20.921us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 14.652us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 54.683us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 28.004us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 20.921us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 14.652us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 54.683us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 28.004us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 4.000s | 3357.577us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.514us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 424.135us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.514us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 424.135us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 19.000s | 1024.684us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 19.000s | 1024.684us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 14.652us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 18.000s | 3618.069us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 18.000s | 3618.069us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 18.000s | 3618.069us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 1744.701us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_mubi_enc_err | 2.000s | 116.922us | 8 | 8 | 100.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 4.000s | 3357.577us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 8 | 8 | 100.00 | |||
| sram_ctrl_readback_err | 2.000s | 43.965us | 8 | 8 | 100.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 85.871us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 85.871us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 18.000s | 3618.069us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.514us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 1744.701us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.514us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.514us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 85.871us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1448.514us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 7 | 8 | 87.50 | |||
| sram_ctrl_stress_all_with_rand_reset | 103.000s | 5333.575us | 7 | 8 | 87.50 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) | 1 test run | |||
| sram_ctrl_stress_all_with_rand_reset | 49873019891485616763008043672712342038155781674677870099434957965182359180982 | 179 |
UVM_INFO @ 794327188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (sram_ctrl_base_vseq.sv:177) [sram_ctrl_common_vseq] Timed out waiting for initialization done | 1 test run | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 44746975041482594193760271252294224812099051508427733910959989209787342437868 | 85 |
UVM_INFO @ 10011037113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|