| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| aon_timer_smoke | 1.540s | 0.000us | 5 | 5 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.750s | 0.000us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| aon_timer_csr_rw | 1.330s | 0.000us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| aon_timer_csr_bit_bash | 4.700s | 0.000us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| aon_timer_csr_aliasing | 1.030s | 0.000us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 1.180s | 0.000us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| aon_timer_csr_rw | 1.330s | 0.000us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 1.030s | 0.000us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| aon_timer_mem_walk | 1.040s | 0.000us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| aon_timer_mem_partial_access | 1.080s | 0.000us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 15 | 15 | 100.00 | |||
| aon_timer_prescaler | 49.830s | 0.000us | 15 | 15 | 100.00 | |
| jump | 5 | 5 | 100.00 | |||
| aon_timer_jump | 1.850s | 0.000us | 5 | 5 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| aon_timer_stress_all | 193.440s | 0.000us | 15 | 15 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| aon_timer_alert_test | 1.950s | 0.000us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| aon_timer_intr_test | 1.210s | 0.000us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| aon_timer_tl_errors | 2.300s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| aon_timer_tl_errors | 2.300s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.750s | 0.000us | 5 | 5 | 100.00 | |
| aon_timer_csr_rw | 1.330s | 0.000us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 1.030s | 0.000us | 5 | 5 | 100.00 | |
| aon_timer_same_csr_outstanding | 2.940s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.750s | 0.000us | 5 | 5 | 100.00 | |
| aon_timer_csr_rw | 1.330s | 0.000us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 1.030s | 0.000us | 5 | 5 | 100.00 | |
| aon_timer_same_csr_outstanding | 2.940s | 0.000us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| aon_timer_tl_intg_err | 11.060s | 0.000us | 20 | 20 | 100.00 | |
| aon_timer_sec_cm | 14.680s | 0.000us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| aon_timer_tl_intg_err | 11.060s | 0.000us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_max_thold | 1.820s | 0.000us | 5 | 5 | 100.00 | |
| min_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_min_thold | 2.090s | 0.000us | 5 | 5 | 100.00 | |
| wkup_count_hi_cdc | 5 | 5 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 11.220s | 0.000us | 5 | 5 | 100.00 | |
| custom_intr | 10 | 10 | 100.00 | |||
| aon_timer_custom_intr | 2.280s | 0.000us | 10 | 10 | 100.00 | |
| alternating_on_off | 5 | 5 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 13.770s | 0.000us | 5 | 5 | 100.00 | |
| stress_all_with_rand_reset | 15 | 15 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 54.210s | 0.000us | 15 | 15 | 100.00 | |