Simulation Results

Simulation Results: flash_ctrl

22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.96 %

code
95.66 %

assert
96.76 %

func
98.45 %

line
96.11 %

branch
97.45 %

cond
94.92 %

toggle
98.66 %

FSM
91.16 %

Validation stages

V1		100.00%
V2		99.30%
V2S		99.51%
V3		100.00%
unmapped		100.00%

145/145 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	143.890s	0.000us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	27.400s	0.000us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	24.470s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	17.970s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	86.050s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	51.560s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	19.140s	0.000us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	17.970s	0.000us	20	20	100.00
	flash_ctrl_csr_aliasing	51.560s	0.000us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	12.710s	0.000us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	9.330s	0.000us	5	5	100.00

1128/1136 passed

99.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	19.710s	0.000us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	101.280s	0.000us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1770.690s	0.000us	3	3	100.00
	flash_ctrl_hw_rma_reset	819.290s	0.000us	20	20	100.00
	flash_ctrl_lcmgr_intg	13.650s	0.000us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	2118.480s	0.000us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	331.260s	0.000us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	207.500s	0.000us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	3318.260s	0.000us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	95.780s	0.000us	5	5	100.00
rd_buff_eviction_w_ecc				97	100	97.00
	flash_ctrl_rw_evict	33.310s	0.000us	37	40	92.50
	flash_ctrl_rw_evict_all_en	33.980s	0.000us	40	40	100.00
	flash_ctrl_re_evict	37.820s	0.000us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	234.020s	0.000us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	234.020s	0.000us	20	20	100.00
memory_protection				19	20	95.00
	flash_ctrl_mp_regions	772.050s	0.000us	19	20	95.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	24.130s	0.000us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	633.990s	0.000us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	778.220s	0.000us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	540.700s	0.000us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1930.930s	0.000us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	14.000s	0.000us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	204.340s	0.000us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	23.210s	0.000us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	17.550s	0.000us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	703.270s	0.000us	5	5	100.00
secret_partition				129	130	99.23
	flash_ctrl_hw_sec_otp	208.660s	0.000us	50	50	100.00
	flash_ctrl_otp_reset	133.620s	0.000us	79	80	98.75
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1770.690s	0.000us	3	3	100.00
interrupts				100	100	100.00
	flash_ctrl_intr_rd	230.510s	0.000us	40	40	100.00
	flash_ctrl_intr_wr	103.230s	0.000us	10	10	100.00
	flash_ctrl_intr_rd_slow_flash	391.870s	0.000us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	317.330s	0.000us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	84.900s	0.000us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	71.230s	0.000us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	23.590s	0.000us	5	5	100.00
	flash_ctrl_ro_derr	138.640s	0.000us	10	10	100.00
	flash_ctrl_rw_derr	241.100s	0.000us	10	10	100.00
	flash_ctrl_derr_detect	170.880s	0.000us	5	5	100.00
	flash_ctrl_integrity	609.640s	0.000us	5	5	100.00
single_bit_err				24	25	96.00
	flash_ctrl_read_word_sweep_serr	19.550s	0.000us	5	5	100.00
	flash_ctrl_ro_serr	130.440s	0.000us	10	10	100.00
	flash_ctrl_rw_serr	237.000s	0.000us	9	10	90.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	86.350s	0.000us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	81.300s	0.000us	5	5	100.00
scramble				60	62	96.77
	flash_ctrl_wo	216.650s	0.000us	20	20	100.00
	flash_ctrl_write_word_sweep	14.810s	0.000us	1	1	100.00
	flash_ctrl_read_word_sweep	9.520s	0.000us	1	1	100.00
	flash_ctrl_ro	113.070s	0.000us	20	20	100.00
	flash_ctrl_rw	537.720s	0.000us	18	20	90.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	37.370s	0.000us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	1017.610s	0.000us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	243.190s	0.000us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	14.550s	0.000us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	13.320s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	21.110s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	21.110s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	24.470s	0.000us	5	5	100.00
	flash_ctrl_csr_rw	17.970s	0.000us	20	20	100.00
	flash_ctrl_csr_aliasing	51.560s	0.000us	5	5	100.00
	flash_ctrl_same_csr_outstanding	33.620s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	24.470s	0.000us	5	5	100.00
	flash_ctrl_csr_rw	17.970s	0.000us	20	20	100.00
	flash_ctrl_csr_aliasing	51.560s	0.000us	5	5	100.00
	flash_ctrl_same_csr_outstanding	33.620s	0.000us	20	20	100.00

V2S

819/823 passed

99.51 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	59.000s	0.000us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	59.000s	0.000us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	59.000s	0.000us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	59.000s	0.000us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	50.520s	0.000us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_tl_intg_err	675.710s	0.000us	20	20	100.00
	flash_ctrl_sec_cm	2456.830s	0.000us	5	5	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	675.710s	0.000us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	675.710s	0.000us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	28.050s	0.000us	3	3	100.00
	flash_ctrl_wr_intg	13.140s	0.000us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	143.890s	0.000us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				259	260	99.62
	flash_ctrl_otp_reset	133.620s	0.000us	79	80	98.75
	flash_ctrl_disable	23.210s	0.000us	50	50	100.00
	flash_ctrl_sec_info_access	77.470s	0.000us	50	50	100.00
	flash_ctrl_connect	17.550s	0.000us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	12.610s	0.000us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	17.970s	0.000us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	59.000s	0.000us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	17.970s	0.000us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	59.000s	0.000us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	17.970s	0.000us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	59.000s	0.000us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	23.210s	0.000us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	28.050s	0.000us	3	3	100.00
	flash_ctrl_access_after_disable	13.660s	0.000us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	30.640s	0.000us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	23.210s	0.000us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	24.130s	0.000us	10	10	100.00
sec_cm_mem_scramble				18	20	90.00
	flash_ctrl_rw	537.720s	0.000us	18	20	90.00
sec_cm_mem_integrity				24	25	96.00
	flash_ctrl_rw_serr	237.000s	0.000us	9	10	90.00
	flash_ctrl_rw_derr	241.100s	0.000us	10	10	100.00
	flash_ctrl_integrity	609.640s	0.000us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1770.690s	0.000us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2456.830s	0.000us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2456.830s	0.000us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2456.830s	0.000us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2456.830s	0.000us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	22.420s	0.000us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_host_grant_err	14.550s	0.000us	5	5	100.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	14.410s	0.000us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2456.830s	0.000us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2456.830s	0.000us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2456.830s	0.000us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	19.530s	0.000us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	368.710s	0.000us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes
	flash_ctrl_rw	66407377995782960768229992182959968425790983968922648357709610025104253221492	None	Job timed out after 60 minutes
	flash_ctrl_rw_serr	43525775038311817544278417587303110146903611669188420918315175200143364900733	None	Job timed out after 60 minutes
	flash_ctrl_rw	110938455665320166027684104347362039665741985818964112590133471052062391138142	None	Job timed out after 60 minutes
UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:188) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:*
	flash_ctrl_mp_regions	10029847366768197320129346936175121554547095475140511351822005794294888581301	163	UVM_FATAL @ 225622.8 ns: (flash_ctrl_mp_regions_vseq.sv:188) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:2 exp_alert_cnt:3 UVM_INFO @ 225622.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:
	flash_ctrl_rw_evict	8780651269077555306935391162171571067963337519293206289356205306011556898755	108	UVM_ERROR @ 10434.7 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 10434.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value:
	flash_ctrl_rw_evict	89803105913747751888948776043302196784081090781134975038037870208517820867140	108	UVM_ERROR @ 34743.7 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0 UVM_INFO @ 34743.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	26066295097358540382275802884125335883764324605620483384259088163384662633012	108	UVM_ERROR @ 12183.3 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0 UVM_INFO @ 12183.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'dst_req_o'
	flash_ctrl_otp_reset	55240790550760689673257376153310330278650005492322959934685619526268880338494	152	Offending 'dst_req_o' UVM_ERROR @ 10011.8 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 10011.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---