Simulation Results: rom_ctrl/32kb

 
22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.86%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.700s 0.000us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 7.230s 0.000us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 7.100s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 7.380s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 6.270s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.840s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 7.100s 0.000us 20 20 100.00
rom_ctrl_csr_aliasing 6.270s 0.000us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 6.380s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.810s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.320s 0.000us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 24.900s 0.000us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 12.150s 0.000us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 9.550s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 12.370s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 12.370s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.230s 0.000us 5 5 100.00
rom_ctrl_csr_rw 7.100s 0.000us 20 20 100.00
rom_ctrl_csr_aliasing 6.270s 0.000us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.470s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.230s 0.000us 5 5 100.00
rom_ctrl_csr_rw 7.100s 0.000us 20 20 100.00
rom_ctrl_csr_aliasing 6.270s 0.000us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.470s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 117.300s 0.000us 19 20 95.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.570s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 324.150s 0.000us 5 5 100.00
rom_ctrl_tl_intg_err 65.400s 0.000us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 324.150s 0.000us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 324.150s 0.000us 5 5 100.00
sec_cm_checker_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 117.300s 0.000us 19 20 95.00
sec_cm_checker_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 117.300s 0.000us 19 20 95.00
sec_cm_checker_fsm_local_esc 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 117.300s 0.000us 19 20 95.00
sec_cm_compare_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 117.300s 0.000us 19 20 95.00
sec_cm_compare_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 117.300s 0.000us 19 20 95.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 324.150s 0.000us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 324.150s 0.000us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.700s 0.000us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.700s 0.000us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.700s 0.000us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 65.400s 0.000us 20 20 100.00
sec_cm_bus_local_esc 21 22 95.45
rom_ctrl_corrupt_sig_fatal_chk 117.300s 0.000us 19 20 95.00
rom_ctrl_kmac_err_chk 12.150s 0.000us 2 2 100.00
sec_cm_mux_mubi 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 117.300s 0.000us 19 20 95.00
sec_cm_mux_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 117.300s 0.000us 19 20 95.00
sec_cm_ctrl_redun 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 117.300s 0.000us 19 20 95.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.570s 0.000us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 324.150s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 547.510s 0.000us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 90774128479344892353676899015301755264263740726837153464437565817194773135934 78
UVM_ERROR @ 492711045 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 492711045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---