| V1 |
|
100.00% |
| V2 |
|
94.06% |
| V2S |
|
100.00% |
| V3 |
|
52.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.460s | 0.000us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.640s | 0.000us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.720s | 0.000us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.550s | 0.000us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 0.770s | 0.000us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.300s | 0.000us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.720s | 0.000us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.770s | 0.000us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 1 | 20 | 5.00 | |||
| rv_timer_random_reset | 9.290s | 0.000us | 1 | 20 | 5.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 3.200s | 0.000us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 550.670s | 0.000us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 550.670s | 0.000us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 4.600s | 0.000us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.820s | 0.000us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.760s | 0.000us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.060s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.060s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.640s | 0.000us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.720s | 0.000us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.770s | 0.000us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.860s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.640s | 0.000us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.720s | 0.000us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.770s | 0.000us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.860s | 0.000us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.340s | 0.000us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.210s | 0.000us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.210s | 0.000us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 4 | 10 | 40.00 | |||
| rv_timer_min | 1.340s | 0.000us | 4 | 10 | 40.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.090s | 0.000us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 17 | 20 | 85.00 | |||
| rv_timer_stress_all_with_rand_reset | 63.850s | 0.000us | 17 | 20 | 85.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 61651912489962971643353337608358145013951408999004175031384846447935828858984 | 75 |
UVM_ERROR @ 85711479 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 85711479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 92715080095828322266283434647410145249649258738407603473596263641714903628330 | 75 |
UVM_ERROR @ 304672212 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 304672212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 113074559755005690127725955027266124543078039915265856244551669063670968488093 | 75 |
UVM_ERROR @ 348510206 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 348510206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 73110361904151483731652226901506574750077202855402759482033642522862077027838 | 75 |
UVM_ERROR @ 84907570 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 84907570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 22261664607220884124356717047382062848159977227914411496985814442769497118649 | 75 |
UVM_ERROR @ 176105621 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 176105621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 74337977830822342980144374259067422702088366745976229538452161691430734183290 | 75 |
UVM_ERROR @ 44831023 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44831023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 41064886460397722389739991590658220796442223804120351027520762660626220490308 | 75 |
UVM_ERROR @ 45352444 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 45352444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 54891794482645295265716228260537217196632503796225690256572221983933208564726 | 75 |
UVM_ERROR @ 216600405 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 216600405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 52505009147247667783913146802257909730300735865252570652159962046825088257546 | 75 |
UVM_ERROR @ 167861914 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 167861914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_random_reset | 49764653488274754569251177091734888965841563843393527888025313003217145651304 | 76 |
UVM_FATAL @ 1551942411 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x454a7f04) == 0x1
UVM_INFO @ 1551942411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 4916587865697776111160999715651104724694413082025791012577863015727646128466 | 76 |
UVM_FATAL @ 231330480 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3c580304) == 0x1
UVM_INFO @ 231330480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 110530594432595973999388912584332244508513300162779772252493587646026667722286 | 75 |
UVM_FATAL @ 442065997 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4f923f04) == 0x1
UVM_INFO @ 442065997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 16127540584748678747100599590637956829249227694146137355040471443149239844071 | 75 |
UVM_FATAL @ 220881870 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x376b1504) == 0x1
UVM_INFO @ 220881870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 44810970593884402542846945001140243822044716805987439095502254828886517855681 | 76 |
UVM_FATAL @ 5623318409 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc3b61904) == 0x1
UVM_INFO @ 5623318409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 74427723627186365234471040503811381959442164447856527971538360159389005332834 | 77 |
UVM_FATAL @ 70386499 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xed9eb904) == 0x1
UVM_INFO @ 70386499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 26424091755855256508313024147075613773588533451871475514805548909469247676173 | 76 |
UVM_FATAL @ 934040100 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x332f8104) == 0x1
UVM_INFO @ 934040100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 95875491428160692887978217609798487640636748830313781846143390477813361204561 | 76 |
UVM_FATAL @ 202400287 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x35dab104) == 0x1
UVM_INFO @ 202400287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 99925461464818326935377806285233228404747542129807693632300850614246688987724 | 78 |
UVM_FATAL @ 117999023 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xafd7e504) == 0x1
UVM_INFO @ 117999023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 73101922243451847732734389851659790197885696123770766828515092969734711961127 | 75 |
UVM_FATAL @ 288857410 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3ebb3504) == 0x1
UVM_INFO @ 288857410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 69457986734905616584843430886446598094879609824709078774594397102999962202636 | 76 |
UVM_FATAL @ 1102187109 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3f1f2704) == 0x1
UVM_INFO @ 1102187109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 93072285471415523870401289163605155099604387689602230333377267109791605821964 | 76 |
UVM_FATAL @ 79120199 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc8c91b04) == 0x1
UVM_INFO @ 79120199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 64959950524729588895173438424762368049479882134429124750707006683311035633329 | 78 |
UVM_FATAL @ 374496593 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4800ab04) == 0x1
UVM_INFO @ 374496593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 21081630874043553298751948025673120532000373638655344861908350447023188754596 | 77 |
UVM_FATAL @ 1329803333 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf68db104) == 0x1
UVM_INFO @ 1329803333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 96552344270786898049275198516138569158334047789341914601547741721694593511702 | 75 |
UVM_FATAL @ 115344632 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2857a304) == 0x1
UVM_INFO @ 115344632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 21872835590618098339383584710105845065610779242140292340025168637134115996320 | 75 |
UVM_FATAL @ 144736022 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe0aebd04) == 0x1
UVM_INFO @ 144736022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 106411373940364160302133746751324904213150132882937315185508770519482506728418 | 76 |
UVM_FATAL @ 196544361 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x85949d04) == 0x1
UVM_INFO @ 196544361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 87016096095310091831492070827457050955779925378072908488427352890190238997621 | 75 |
UVM_FATAL @ 210815467 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x63f18f04) == 0x1
UVM_INFO @ 210815467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 51244019881820626370743578834960697695504130922302768196937496613675734431486 | 75 |
UVM_FATAL @ 86168415 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x33a02904) == 0x1
UVM_INFO @ 86168415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 48623126029546746399785612556138088618910394346362796589548693309047495345975 | 75 |
UVM_FATAL @ 276631795 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4e547f04) == 0x1
UVM_INFO @ 276631795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 51416054313001176644681949122258001182394306295556036543519833525963593089586 | 75 |
UVM_FATAL @ 545306877 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa9c4f04) == 0x1
UVM_INFO @ 545306877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 2105047796785658024413482783745264120597434248811950420464230386223106332035 | 75 |
UVM_FATAL @ 5584289543 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x31e62d04) == 0x1
UVM_INFO @ 5584289543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 90677250898596348691860384942870321782422969387895070588157334273870916862215 | 75 |
UVM_FATAL @ 101320688 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7cdcd104) == 0x1
UVM_INFO @ 101320688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 94329719347327786627510468339786902162851767885239447329343175605389123129542 | 76 |
UVM_FATAL @ 1056351910 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7659ef04) == 0x1
UVM_INFO @ 1056351910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 10128448235454406476783053161151025073797445168844073464049126841557062065048 | 75 |
UVM_FATAL @ 255226239 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2228d304) == 0x1
UVM_INFO @ 255226239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | ||||
| rv_timer_max | 73409064394898660748622464789879847046030011154599202790227736387481887516414 | 75 |
UVM_ERROR @ 237032759 ps: (rv_timer_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
UVM_INFO @ 237032759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 44696884020209423344696604873245582740211249394025257290107731595685594777219 | 129 |
UVM_ERROR @ 2676960755 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2676960755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 34857949787720750972699443848627635907027768266121246796555978968095005455925 | 327 |
UVM_ERROR @ 1168792737 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1168792737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 69619147618175689129411474125140877677544511939247712066565871466903142924407 | 374 |
UVM_FATAL @ 5198494279 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 5198494279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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