Simulation Results: spi_device/2p

 
22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.09 %
  • code
  • 94.28 %
  • assert
  • 94.74 %
  • func
  • 99.26 %
  • line
  • 99.16 %
  • branch
  • 98.49 %
  • cond
  • 96.65 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
99.86%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_device_flash_and_tpm 584.310s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.640s 0.000us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 2.570s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 26.230s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 18.820s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 4.030s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 2.570s 0.000us 20 20 100.00
spi_device_csr_aliasing 18.820s 0.000us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 1.010s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 2.540s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.200s 0.000us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.490s 0.000us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.080s 0.000us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 5.770s 0.000us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 5.770s 0.000us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 25.430s 0.000us 50 50 100.00
spi_device_tpm_sts_read 1.430s 0.000us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 40.430s 0.000us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 48.900s 0.000us 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 35.620s 0.000us 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 35.620s 0.000us 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 27.570s 0.000us 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 27.570s 0.000us 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 27.570s 0.000us 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 27.570s 0.000us 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 27.570s 0.000us 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
flash_cmd_upload 50 50 100.00
spi_device_upload 80.120s 0.000us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 110.010s 0.000us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 110.010s 0.000us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 110.010s 0.000us 50 50 100.00
cmd_read_buffer 99 100 99.00
spi_device_flash_mode 47.740s 0.000us 49 50 98.00
spi_device_read_buffer_direct 15.570s 0.000us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 110.010s 0.000us 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 359.770s 0.000us 50 50 100.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 31.800s 0.000us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 31.800s 0.000us 50 50 100.00
TPM_with_flash_or_passthrough_mode 50 50 100.00
spi_device_flash_and_tpm 584.310s 0.000us 50 50 100.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 554.730s 0.000us 50 50 100.00
stress_all 48 50 96.00
spi_device_stress_all 570.270s 0.000us 48 50 96.00
alert_test 50 50 100.00
spi_device_alert_test 1.100s 0.000us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.120s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 4.780s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 4.780s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.640s 0.000us 5 5 100.00
spi_device_csr_rw 2.570s 0.000us 20 20 100.00
spi_device_csr_aliasing 18.820s 0.000us 5 5 100.00
spi_device_same_csr_outstanding 4.080s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.640s 0.000us 5 5 100.00
spi_device_csr_rw 2.570s 0.000us 20 20 100.00
spi_device_csr_aliasing 18.820s 0.000us 5 5 100.00
spi_device_same_csr_outstanding 4.080s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_tl_intg_err 19.830s 0.000us 20 20 100.00
spi_device_sec_cm 1.580s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 19.830s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
spi_device_flash_mode_ignore_cmds 434.920s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2815) [scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == * (* [*] vs * [*])
spi_device_flash_mode 74285360743330289904114268499918679321963272317616837334654162268455720583420 76
UVM_ERROR @ 3121787265 ps: (spi_device_scoreboard.sv:2815) [uvm_test_top.env.scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3121787265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *
spi_device_stress_all 113041014771104241662058234602550947200338728437389485951591152073107171111040 98
UVM_ERROR @ 3144096971 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (10610688 [0xa1e800] vs 1 [0x1]) CSR last_read_addr compare mismatch act 0xa1e800 != exp 0x1
tl_ul_fuzzy_flash_status_q[i] = 0x64e7cc
tl_ul_fuzzy_flash_status_q[i] = 0xe06324
tl_ul_fuzzy_flash_status_q[i] = 0x150c84
tl_ul_fuzzy_flash_status_q[i] = 0x205d70
spi_device_stress_all 99689272247824303098563035494643859302507776658711199768259692340511326837205 188
UVM_ERROR @ 139250861197 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (16066560 [0xf52800] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xf52800 != exp 0x0
UVM_INFO @ 139597795564 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/12
UVM_INFO @ 139597795564 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 5/12
UVM_INFO @ 140071117759 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/14
UVM_INFO @ 148817209532 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 5/12