Simulation Results

Simulation Results: spi_host

22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.82 %

code
95.06 %

assert
95.64 %

func
90.76 %

block
97.00 %

line
98.76 %

branch
93.45 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.82%
V2S		100.00%
unmapped		100.00%

140/140 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	119.000s	0.000us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	2.000s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	2.000s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	4.000s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	2.000s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	3.000s	0.000us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	2.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	2.000s	0.000us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	2.000s	0.000us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	2.000s	0.000us	5	5	100.00

1138/1140 passed

99.82 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	29.000s	0.000us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	30.000s	0.000us	50	50	100.00
	spi_host_error_cmd	29.000s	0.000us	50	50	100.00
	spi_host_event	826.000s	0.000us	50	50	100.00
clock_rate				50	50	100.00
	spi_host_speed	30.000s	0.000us	50	50	100.00
speed				50	50	100.00
	spi_host_speed	30.000s	0.000us	50	50	100.00
chip_select_timing				50	50	100.00
	spi_host_speed	30.000s	0.000us	50	50	100.00
sw_reset				50	50	100.00
	spi_host_sw_reset	353.000s	0.000us	50	50	100.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	28.000s	0.000us	50	50	100.00
cpol_cpha				50	50	100.00
	spi_host_speed	30.000s	0.000us	50	50	100.00
full_cycle				50	50	100.00
	spi_host_speed	30.000s	0.000us	50	50	100.00
duplex				50	50	100.00
	spi_host_smoke	119.000s	0.000us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	119.000s	0.000us	50	50	100.00
stress_all				49	50	98.00
	spi_host_stress_all	140.000s	0.000us	49	50	98.00
spien				50	50	100.00
	spi_host_spien	134.000s	0.000us	50	50	100.00
stall				49	50	98.00
	spi_host_status_stall	1221.000s	0.000us	49	50	98.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	44.000s	0.000us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	30.000s	0.000us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	20.000s	0.000us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	2.000s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	4.000s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	4.000s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	0.000us	5	5	100.00
	spi_host_csr_rw	2.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	2.000s	0.000us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	0.000us	5	5	100.00
	spi_host_csr_rw	2.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	2.000s	0.000us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	0.000us	20	20	100.00

V2S

45/45 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_sec_cm	22.000s	0.000us	5	5	100.00
	spi_host_tl_intg_err	3.000s	0.000us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	3.000s	0.000us	20	20	100.00

unmapped

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				10	10	100.00
	spi_host_upper_range_clkdiv	381.000s	0.000us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = ns spi_host_reg_block.status.rxqd (addr=, Comparison=CompareOpEq, exp_data=, call_count=
	spi_host_stress_all	16026840696341257903554512530447829113334554323149282951177823229305282910546	167	UVM_FATAL @ 10053813943 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x8f4c54d4, Comparison=CompareOpEq, exp_data=0x0, call_count=22 UVM_INFO @ 10053813943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed
	spi_host_status_stall	53632985223017185447671746061607153398384191691578421540127720885739966346938	8770	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 18286501208 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed UVM_ERROR @ 18286501208 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=18286501000 ps UVM_INFO @ 18286501208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---