Simulation Results: aes/masked

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.28 %
  • code
  • 98.16 %
  • assert
  • 98.43 %
  • func
  • 95.26 %
  • block
  • 98.23 %
  • line
  • 99.42 %
  • branch
  • 95.08 %
  • toggle
  • 98.13 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.93%
V2S
95.18%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 0.000us 1 1 100.00
smoke 50 50 100.00
aes_smoke 9.000s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 3.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 7.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 4.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 0.000us 20 20 100.00
aes_csr_aliasing 4.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 9.000s 0.000us 50 50 100.00
aes_config_error 11.000s 0.000us 50 50 100.00
aes_stress 125.000s 0.000us 50 50 100.00
key_length 150 150 100.00
aes_smoke 9.000s 0.000us 50 50 100.00
aes_config_error 11.000s 0.000us 50 50 100.00
aes_stress 125.000s 0.000us 50 50 100.00
back2back 100 100 100.00
aes_stress 125.000s 0.000us 50 50 100.00
aes_b2b 23.000s 0.000us 50 50 100.00
backpressure 50 50 100.00
aes_stress 125.000s 0.000us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 9.000s 0.000us 50 50 100.00
aes_config_error 11.000s 0.000us 50 50 100.00
aes_stress 125.000s 0.000us 50 50 100.00
aes_alert_reset 58.000s 0.000us 50 50 100.00
failure_test 150 150 100.00
aes_man_cfg_err 7.000s 0.000us 50 50 100.00
aes_config_error 11.000s 0.000us 50 50 100.00
aes_alert_reset 58.000s 0.000us 50 50 100.00
trigger_clear_test 49 50 98.00
aes_clear 27.000s 0.000us 49 50 98.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 12.000s 0.000us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 6.000s 0.000us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 58.000s 0.000us 50 50 100.00
stress 50 50 100.00
aes_stress 125.000s 0.000us 50 50 100.00
sideload 100 100 100.00
aes_stress 125.000s 0.000us 50 50 100.00
aes_sideload 16.000s 0.000us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 99.000s 0.000us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 61.000s 0.000us 10 10 100.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 12.000s 0.000us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 3.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 3.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 3.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 3.000s 0.000us 5 5 100.00
aes_csr_rw 3.000s 0.000us 20 20 100.00
aes_csr_aliasing 4.000s 0.000us 5 5 100.00
aes_same_csr_outstanding 3.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 3.000s 0.000us 5 5 100.00
aes_csr_rw 3.000s 0.000us 20 20 100.00
aes_csr_aliasing 4.000s 0.000us 5 5 100.00
aes_same_csr_outstanding 3.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 72.000s 0.000us 50 50 100.00
fault_inject 657 700 93.86
aes_fi 2025.000s 0.000us 48 50 96.00
aes_control_fi 58.000s 0.000us 279 300 93.00
aes_cipher_fi 59.000s 0.000us 330 350 94.29
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 34.000s 0.000us 5 5 100.00
aes_tl_intg_err 4.000s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 4.000s 0.000us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 58.000s 0.000us 50 50 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
sec_cm_main_config_sparse 219 220 99.55
aes_smoke 9.000s 0.000us 50 50 100.00
aes_stress 125.000s 0.000us 50 50 100.00
aes_alert_reset 58.000s 0.000us 50 50 100.00
aes_core_fi 30.000s 0.000us 69 70 98.57
sec_cm_gcm_config_sparse 269 270 99.63
aes_gcm_save_restore 12.000s 0.000us 100 100 100.00
aes_config_error 11.000s 0.000us 50 50 100.00
aes_stress 125.000s 0.000us 50 50 100.00
aes_core_fi 30.000s 0.000us 69 70 98.57
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 0.000us 20 20 100.00
sec_cm_aux_config_regwen 99 100 99.00
aes_readability 5.000s 0.000us 49 50 98.00
aes_stress 125.000s 0.000us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 125.000s 0.000us 50 50 100.00
aes_sideload 16.000s 0.000us 50 50 100.00
sec_cm_key_sw_unreadable 49 50 98.00
aes_readability 5.000s 0.000us 49 50 98.00
sec_cm_data_reg_sw_unreadable 49 50 98.00
aes_readability 5.000s 0.000us 49 50 98.00
sec_cm_key_sec_wipe 49 50 98.00
aes_readability 5.000s 0.000us 49 50 98.00
sec_cm_iv_config_sec_wipe 49 50 98.00
aes_readability 5.000s 0.000us 49 50 98.00
sec_cm_data_reg_sec_wipe 49 50 98.00
aes_readability 5.000s 0.000us 49 50 98.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 125.000s 0.000us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 125.000s 0.000us 50 50 100.00
sec_cm_main_fsm_sparse 48 50 96.00
aes_fi 2025.000s 0.000us 48 50 96.00
sec_cm_main_fsm_redun 707 750 94.27
aes_fi 2025.000s 0.000us 48 50 96.00
aes_control_fi 58.000s 0.000us 279 300 93.00
aes_cipher_fi 59.000s 0.000us 330 350 94.29
aes_ctr_fi 6.000s 0.000us 50 50 100.00
sec_cm_cipher_fsm_sparse 48 50 96.00
aes_fi 2025.000s 0.000us 48 50 96.00
sec_cm_cipher_fsm_redun 657 700 93.86
aes_fi 2025.000s 0.000us 48 50 96.00
aes_control_fi 58.000s 0.000us 279 300 93.00
aes_cipher_fi 59.000s 0.000us 330 350 94.29
sec_cm_cipher_ctr_redun 330 350 94.29
aes_cipher_fi 59.000s 0.000us 330 350 94.29
sec_cm_ctr_fsm_sparse 48 50 96.00
aes_fi 2025.000s 0.000us 48 50 96.00
sec_cm_ctr_fsm_redun 377 400 94.25
aes_fi 2025.000s 0.000us 48 50 96.00
aes_control_fi 58.000s 0.000us 279 300 93.00
aes_ctr_fi 6.000s 0.000us 50 50 100.00
sec_cm_ghash_fsm_sparse 48 50 96.00
aes_fi 2025.000s 0.000us 48 50 96.00
sec_cm_ctrl_sparse 707 750 94.27
aes_fi 2025.000s 0.000us 48 50 96.00
aes_control_fi 58.000s 0.000us 279 300 93.00
aes_cipher_fi 59.000s 0.000us 330 350 94.29
aes_ctr_fi 6.000s 0.000us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 58.000s 0.000us 50 50 100.00
sec_cm_main_fsm_local_esc 707 750 94.27
aes_fi 2025.000s 0.000us 48 50 96.00
aes_control_fi 58.000s 0.000us 279 300 93.00
aes_cipher_fi 59.000s 0.000us 330 350 94.29
aes_ctr_fi 6.000s 0.000us 50 50 100.00
sec_cm_cipher_fsm_local_esc 707 750 94.27
aes_fi 2025.000s 0.000us 48 50 96.00
aes_control_fi 58.000s 0.000us 279 300 93.00
aes_cipher_fi 59.000s 0.000us 330 350 94.29
aes_ctr_fi 6.000s 0.000us 50 50 100.00
sec_cm_ctr_fsm_local_esc 377 400 94.25
aes_fi 2025.000s 0.000us 48 50 96.00
aes_control_fi 58.000s 0.000us 279 300 93.00
aes_ctr_fi 6.000s 0.000us 50 50 100.00
sec_cm_ghash_fsm_local_esc 138 140 98.57
aes_fi 2025.000s 0.000us 48 50 96.00
aes_ghash_fi 4.000s 0.000us 90 90 100.00
sec_cm_data_reg_local_esc 657 700 93.86
aes_fi 2025.000s 0.000us 48 50 96.00
aes_control_fi 58.000s 0.000us 279 300 93.00
aes_cipher_fi 59.000s 0.000us 330 350 94.29
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 48.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 57751759611245633617285006181808282543632393000012923948738179105525795978551 628
UVM_ERROR @ 2091831147 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2091831147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 52503162372398330758510638521723633843805592050680270540690504177709585139838 442
UVM_ERROR @ 449557369 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 449557369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 705727009146036518153152692291569224600990738985449923541638431914414077695 633
UVM_ERROR @ 1360672768 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1360672768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 1291068639610829300727943688018325488335982448642962796520595952104130714255 454
UVM_ERROR @ 1197131564 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1197131564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 5813464868529976038455847538742588055357635357765758304877645409382029808246 865
UVM_ERROR @ 1363340983 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1363340983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 38785673490669143146413992708526004960606177922633211513614449055221832631251 661
UVM_ERROR @ 5861554742 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 5861554742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1112): Assertion AesModeValid has failed
aes_stress_all_with_rand_reset 21487111405567676055312610191815402521443071905053428045102197276171764819777 187
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1112): (time 32862111 PS) Assertion tb.dut.u_aes_core.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 32862111 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 32862111 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 32862111 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 32862111 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
Job timed out after * minutes
aes_cipher_fi 27227413461059117859688639145949434484011235677295170647772760406884968025400 None
Job timed out after 1 minutes
aes_control_fi 98935083908483060012531895675756664257868957017753420221382846293431772616625 None
Job timed out after 1 minutes
aes_cipher_fi 37344735685603891728305430312189212814074499298453051701550834042763254347045 None
Job timed out after 1 minutes
aes_cipher_fi 16830683527089208011883914870006715799212666491459629372594893295503433324658 None
Job timed out after 1 minutes
aes_cipher_fi 93632257587676300417357012438362292995881081106604179083372212654058621165792 None
Job timed out after 1 minutes
aes_control_fi 101290084428937185192010510704291079516129776559688615797079177945556759203922 None
Job timed out after 1 minutes
aes_control_fi 72281633641849793383181736961142050868488665812829302710558043571622719784887 None
Job timed out after 1 minutes
aes_control_fi 108122569145569071796254787410207020785181919830944792449661574676370642414027 None
Job timed out after 1 minutes
aes_cipher_fi 79581720796761854093867062522209655257297949845086792032897278125299132191032 None
Job timed out after 1 minutes
aes_control_fi 90636254657246287803400531130182505410387640221117874143152187069005507545077 None
Job timed out after 1 minutes
aes_control_fi 27751718446012420775090851039893998647965036364861257067851832763159077471621 None
Job timed out after 1 minutes
aes_control_fi 87147808928500765544767612559444991396159794979149717329963119306845295111990 None
Job timed out after 1 minutes
aes_cipher_fi 105784231752596881254236721126254482215355877668042463383951300933481524575290 None
Job timed out after 1 minutes
aes_control_fi 49330681583966951621622513279076394382919926839219753172760638483808005691387 None
Job timed out after 1 minutes
aes_control_fi 91872684843564905468101088212704510423176058888177375672978731005415379266212 None
Job timed out after 1 minutes
aes_control_fi 36076821509804078792030221179774338025626374544304864830758216345356297819451 None
Job timed out after 1 minutes
aes_control_fi 103192814490905814984247866606262651989806163885135055294593101899471730202940 None
Job timed out after 1 minutes
aes_control_fi 20302584129727649220482272902996852154497103194179240770790375210380874328430 None
Job timed out after 1 minutes
aes_cipher_fi 73343798040627845443462806616319172916407486262518584826768526925421846326815 None
Job timed out after 1 minutes
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_alert_reset_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG
aes_stress_all_with_rand_reset 75765377159331542679737726515627365393973702209382163259444874003710363898893 1178
UVM_FATAL @ 946702675 ps: (aes_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG
UVM_INFO @ 946702675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 75310153525618499027783739332185549735734596096035906312922989963820927789152 172
UVM_FATAL @ 147590788 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 147590788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1136): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS)
aes_stress_all_with_rand_reset 55955421667873355756520051306202801783285871824328015401316381926791753844432 378
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1136): (time 567377562 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 567357154 PS)
($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
|
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1142): (time 567377562 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 567357154 PS)
UVM_ERROR @ 567377562 ps: (aes_core.sv:1136) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 81709357161061412452410175442125137262173897169179136958119038391495510110327 149
UVM_FATAL @ 10015765072 ps: (aes_core_fi_vseq.sv:70) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10015765072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:775) scoreboard [scoreboard] # *
aes_fi 17563834809361705989165770234710684614590720060160352347115965317012780511902 12447
UVM_FATAL @ 430465018 ps: (aes_scoreboard.sv:775) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] # 0
TEST FAILED MESSAGES DID NOT MATCH
0 4b 6a 00 0
1 00 b4 00 0
aes_clear 60126860414785416257481081201298279173590829255966345602956676414082918064512 11917
UVM_FATAL @ 163871680 ps: (aes_scoreboard.sv:775) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] # 4
TEST FAILED MESSAGES DID NOT MATCH
0 7d d1 0e 0
1 00 a7 be 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 53428054931956817602218847396974883441707559608242705368823601460711377478127 157
UVM_FATAL @ 10014955899 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014955899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 69171919582377364757449999840466150681218836384710080029332928342040181291780 140
UVM_FATAL @ 10002960589 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10002960589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 55392587895924450333155339103774597646080394331143467699147531302448468500590 148
UVM_FATAL @ 10007030497 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007030497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 99369664282277898271140547318912493929339591486924480234881333044019383295087 147
UVM_FATAL @ 10036305950 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10036305950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 43815439773700985290085852330911232643793406100754898526776838857443710765180 145
UVM_FATAL @ 10010327673 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010327673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 7834332070810271716505063511479434561429908262361152369637222726521350651134 152
UVM_FATAL @ 10077294977 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10077294977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 80716085623250941969327675457641991579352300686745677532521631806362539060718 150
UVM_FATAL @ 10005753737 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10005753737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 4024382201035215475865009640562579266138397941255969873807350731078955769826 158
UVM_FATAL @ 10016751572 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10016751572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 72406556593852000684845414493019198488358929345141898324720694862039118970651 143
UVM_FATAL @ 10006846721 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006846721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_readability_vseq.sv:66) virtual_sequencer [aes_readability_vseq] ----|Write data reg was Readable |----
aes_readability 66137165819264759251087194881847508651253756116992900224119679015793099105687 138
UVM_FATAL @ 3448819 ps: (aes_readability_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_readability_vseq] ----|Write data reg was Readable |----
UVM_INFO @ 3448819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
aes_fi 77980445692500415894626548428022403031589525508352775457409908209302688950693 23998654
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 18472771873542432696998404704649943102693406140826396161131707723128633679232 145
UVM_FATAL @ 10013498923 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10013498923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 15254502654911496989343596061321072710490440462590615979429202250136601938887 159
UVM_FATAL @ 10004935122 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10004935122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 11103660834389075648440107756096324916831328999551615192947875763491943453220 158
UVM_FATAL @ 10021907874 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10021907874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 18762449108760461397783801631367996239527490587000632033014063278122021072168 156
UVM_FATAL @ 10005681316 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10005681316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 40834711160027664241746714438284146586468858133481443279464379038486425700108 142
UVM_FATAL @ 10047789272 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10047789272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 85491187657827917242380262655539644011962585122735286133488445280239391673321 143
UVM_FATAL @ 10208559129 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10208559129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 86228021367408876567689642742055393500042662646802783238937846089734004385567 148
UVM_FATAL @ 10026748861 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10026748861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 74077803574807800770113418445491450207370181179498902191463522695002959148788 149
UVM_FATAL @ 10011265088 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10011265088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 11790263797185491973945018893911832314587680326118627227327713421014561723716 146
UVM_FATAL @ 10005914047 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10005914047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
aes_cipher_fi 78573559797340074322149002950961760650145307658361942365058083182610288093272 139
UVM_FATAL @ 10018503072 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x9839d684, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10018503072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 77536790382588612329065205711171932359218520156817469122113821648448525960079 141
UVM_FATAL @ 10026589058 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x15d77784, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10026589058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 15008235299024802458052267539797976635325112641506528968154603277350441056829 138
UVM_FATAL @ 10018711209 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xba639384, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10018711209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
aes_cipher_fi 88069991648331021744254737469613619576774198858070195440617202652871103155544 143
UVM_FATAL @ 10088129084 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xdc7cdc84, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10088129084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---