Simulation Results: aes/unmasked

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.13 %
  • code
  • 94.98 %
  • assert
  • 98.13 %
  • func
  • 92.28 %
  • block
  • 95.65 %
  • line
  • 97.30 %
  • branch
  • 91.02 %
  • toggle
  • 97.99 %
  • FSM
  • 93.62 %
Validation stages
V1
100.00%
V2
99.71%
V2S
94.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 0.000us 1 1 100.00
smoke 50 50 100.00
aes_smoke 3.000s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 37.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 37.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 41.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 37.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 37.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 37.000s 0.000us 20 20 100.00
aes_csr_aliasing 37.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 3.000s 0.000us 50 50 100.00
aes_config_error 4.000s 0.000us 50 50 100.00
aes_stress 4.000s 0.000us 50 50 100.00
key_length 150 150 100.00
aes_smoke 3.000s 0.000us 50 50 100.00
aes_config_error 4.000s 0.000us 50 50 100.00
aes_stress 4.000s 0.000us 50 50 100.00
back2back 100 100 100.00
aes_stress 4.000s 0.000us 50 50 100.00
aes_b2b 7.000s 0.000us 50 50 100.00
backpressure 50 50 100.00
aes_stress 4.000s 0.000us 50 50 100.00
multi_message 199 200 99.50
aes_smoke 3.000s 0.000us 50 50 100.00
aes_config_error 4.000s 0.000us 50 50 100.00
aes_stress 4.000s 0.000us 50 50 100.00
aes_alert_reset 4.000s 0.000us 49 50 98.00
failure_test 148 150 98.67
aes_man_cfg_err 3.000s 0.000us 49 50 98.00
aes_config_error 4.000s 0.000us 50 50 100.00
aes_alert_reset 4.000s 0.000us 49 50 98.00
trigger_clear_test 50 50 100.00
aes_clear 3.000s 0.000us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 0.000us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 0.000us 1 1 100.00
reset_recovery 49 50 98.00
aes_alert_reset 4.000s 0.000us 49 50 98.00
stress 50 50 100.00
aes_stress 4.000s 0.000us 50 50 100.00
sideload 100 100 100.00
aes_stress 4.000s 0.000us 50 50 100.00
aes_sideload 4.000s 0.000us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 3.000s 0.000us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 24.000s 0.000us 10 10 100.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 3.000s 0.000us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 2.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 38.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 38.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 37.000s 0.000us 5 5 100.00
aes_csr_rw 37.000s 0.000us 20 20 100.00
aes_csr_aliasing 37.000s 0.000us 5 5 100.00
aes_same_csr_outstanding 37.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 37.000s 0.000us 5 5 100.00
aes_csr_rw 37.000s 0.000us 20 20 100.00
aes_csr_aliasing 37.000s 0.000us 5 5 100.00
aes_same_csr_outstanding 37.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 5.000s 0.000us 50 50 100.00
fault_inject 653 700 93.29
aes_fi 4.000s 0.000us 47 50 94.00
aes_control_fi 42.000s 0.000us 281 300 93.67
aes_cipher_fi 46.000s 0.000us 325 350 92.86
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 37.000s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 37.000s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 37.000s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 37.000s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 38.000s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
aes_tl_intg_err 38.000s 0.000us 20 20 100.00
aes_sec_cm 4.000s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 38.000s 0.000us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 49 50 98.00
aes_alert_reset 4.000s 0.000us 49 50 98.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 37.000s 0.000us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 37.000s 0.000us 20 20 100.00
sec_cm_main_config_sparse 213 220 96.82
aes_smoke 3.000s 0.000us 50 50 100.00
aes_stress 4.000s 0.000us 50 50 100.00
aes_alert_reset 4.000s 0.000us 49 50 98.00
aes_core_fi 30.000s 0.000us 64 70 91.43
sec_cm_gcm_config_sparse 264 270 97.78
aes_gcm_save_restore 3.000s 0.000us 100 100 100.00
aes_config_error 4.000s 0.000us 50 50 100.00
aes_stress 4.000s 0.000us 50 50 100.00
aes_core_fi 30.000s 0.000us 64 70 91.43
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 37.000s 0.000us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 0.000us 50 50 100.00
aes_stress 4.000s 0.000us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 4.000s 0.000us 50 50 100.00
aes_sideload 4.000s 0.000us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 0.000us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 0.000us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 0.000us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 0.000us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 0.000us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 4.000s 0.000us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 4.000s 0.000us 50 50 100.00
sec_cm_main_fsm_sparse 47 50 94.00
aes_fi 4.000s 0.000us 47 50 94.00
sec_cm_main_fsm_redun 702 750 93.60
aes_fi 4.000s 0.000us 47 50 94.00
aes_control_fi 42.000s 0.000us 281 300 93.67
aes_cipher_fi 46.000s 0.000us 325 350 92.86
aes_ctr_fi 3.000s 0.000us 49 50 98.00
sec_cm_cipher_fsm_sparse 47 50 94.00
aes_fi 4.000s 0.000us 47 50 94.00
sec_cm_cipher_fsm_redun 653 700 93.29
aes_fi 4.000s 0.000us 47 50 94.00
aes_control_fi 42.000s 0.000us 281 300 93.67
aes_cipher_fi 46.000s 0.000us 325 350 92.86
sec_cm_cipher_ctr_redun 325 350 92.86
aes_cipher_fi 46.000s 0.000us 325 350 92.86
sec_cm_ctr_fsm_sparse 47 50 94.00
aes_fi 4.000s 0.000us 47 50 94.00
sec_cm_ctr_fsm_redun 377 400 94.25
aes_fi 4.000s 0.000us 47 50 94.00
aes_control_fi 42.000s 0.000us 281 300 93.67
aes_ctr_fi 3.000s 0.000us 49 50 98.00
sec_cm_ghash_fsm_sparse 47 50 94.00
aes_fi 4.000s 0.000us 47 50 94.00
sec_cm_ctrl_sparse 702 750 93.60
aes_fi 4.000s 0.000us 47 50 94.00
aes_control_fi 42.000s 0.000us 281 300 93.67
aes_cipher_fi 46.000s 0.000us 325 350 92.86
aes_ctr_fi 3.000s 0.000us 49 50 98.00
sec_cm_main_fsm_global_esc 49 50 98.00
aes_alert_reset 4.000s 0.000us 49 50 98.00
sec_cm_main_fsm_local_esc 702 750 93.60
aes_fi 4.000s 0.000us 47 50 94.00
aes_control_fi 42.000s 0.000us 281 300 93.67
aes_cipher_fi 46.000s 0.000us 325 350 92.86
aes_ctr_fi 3.000s 0.000us 49 50 98.00
sec_cm_cipher_fsm_local_esc 702 750 93.60
aes_fi 4.000s 0.000us 47 50 94.00
aes_control_fi 42.000s 0.000us 281 300 93.67
aes_cipher_fi 46.000s 0.000us 325 350 92.86
aes_ctr_fi 3.000s 0.000us 49 50 98.00
sec_cm_ctr_fsm_local_esc 377 400 94.25
aes_fi 4.000s 0.000us 47 50 94.00
aes_control_fi 42.000s 0.000us 281 300 93.67
aes_ctr_fi 3.000s 0.000us 49 50 98.00
sec_cm_ghash_fsm_local_esc 137 140 97.86
aes_fi 4.000s 0.000us 47 50 94.00
aes_ghash_fi 3.000s 0.000us 90 90 100.00
sec_cm_data_reg_local_esc 653 700 93.29
aes_fi 4.000s 0.000us 47 50 94.00
aes_control_fi 42.000s 0.000us 281 300 93.67
aes_cipher_fi 46.000s 0.000us 325 350 92.86
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 16.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 81504294501971385392039331631270280245236464683655925133608732193957647867408 883
UVM_ERROR @ 723535682 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 723535682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 21836581061467216178163417750517825177916543922157957123563836142192948894501 448
UVM_ERROR @ 360800221 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 360800221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 102910779186801001440525949335713871167356596846481163281484771739480485641244 1062
UVM_ERROR @ 1193660699 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1193660699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 81389142859916631795694406171065970338692454585145356999519910452610587078587 457
UVM_ERROR @ 236441684 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 236441684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 7162477965066505021107273659850965541065578857663508216999237412521313855644 1188
UVM_ERROR @ 1837107916 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1837107916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 21042365174467841246988413954948918971299074633068415668837500090272012785261 590
UVM_ERROR @ 181042266 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 181042266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 107149230745947903318270995056292245459656346092056963709002470487248521987731 998
UVM_ERROR @ 308976598 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 308976598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
aes_ctr_fi 104022735909689530769452619648357362800953638249701918608056354693882777980015 None
Job timed out after 1 minutes
aes_cipher_fi 34139939226394110922823281113845323390777080844975629856440618143810961808298 None
Job timed out after 1 minutes
aes_cipher_fi 8770234068929210315560309835344716689721552597542312614999431619683467389729 None
Job timed out after 1 minutes
aes_cipher_fi 115053501744696325305463934635525637210580207332606042681695872538508166935183 None
Job timed out after 1 minutes
aes_control_fi 102591833606496617299434476618964656117557694097459364145432004896911881813753 None
Job timed out after 1 minutes
aes_control_fi 77474856199310172487669588225071142251510250958427952319151850514570247155352 None
Job timed out after 1 minutes
aes_control_fi 80014415312034850280421190722045628070835852773453119543139672742883165668466 None
Job timed out after 1 minutes
aes_cipher_fi 39536326038649189902815197534096923752756134713858798286061813182727074438719 None
Job timed out after 1 minutes
aes_cipher_fi 102806129795245070712269377692136248153933520614200953263127068299044600385896 None
Job timed out after 1 minutes
aes_cipher_fi 26883314794856490950761033690732416566227478023938634861829509945023728663552 None
Job timed out after 1 minutes
aes_control_fi 92108543248894133058967535552000144839248252283856614391805838676834304016560 None
Job timed out after 1 minutes
aes_control_fi 85818484132146452035564703417948715099145736194443387559062540905652110616487 None
Job timed out after 1 minutes
aes_control_fi 57832553826923273476366541683755657702182225070004952311052761083255056522367 None
Job timed out after 1 minutes
aes_control_fi 113993582704463930141915705824526413536643553178317793590081290684722892044359 None
Job timed out after 1 minutes
aes_cipher_fi 37598843756867669339094596851995973321383014747755558696901321751442496226084 None
Job timed out after 1 minutes
aes_control_fi 110818788034440243810938673257637246495004328845774256886878523931516203097808 None
Job timed out after 1 minutes
aes_cipher_fi 17095734290609045573774775037190857038677281402042238076335173216706342957826 None
Job timed out after 1 minutes
aes_cipher_fi 42704901891874975397933963087347776528014471424760439269736364643468254910516 None
Job timed out after 1 minutes
aes_control_fi 84546068540608155845572845299072414704589990652480397174802469423492348107877 None
Job timed out after 1 minutes
aes_control_fi 2708777204848050057175634338718283297479164658881085174107800456613518710050 None
Job timed out after 1 minutes
aes_control_fi 284082077121598135395682927142417208031993904032884110401270946982576009582 None
Job timed out after 1 minutes
aes_cipher_fi 70271969472451066296330873768954069065394376043806910906677647663692835384177 None
Job timed out after 1 minutes
aes_cipher_fi 59208740756739765923449338123412196793409193541651060436435055562126946947188 None
Job timed out after 1 minutes
aes_cipher_fi 11145257258340703354141440973426589518593484896491405854373353537527460969377 None
Job timed out after 1 minutes
aes_control_fi 46407566438780702681867737979063970592467257524438733574664439683947961199808 None
Job timed out after 1 minutes
aes_cipher_fi 103600445630606386778843600708988582311449267389186740502476543825315213995196 None
Job timed out after 1 minutes
aes_cipher_fi 26035976124964708138934292130681506958997385425836074948369053786549624484510 None
Job timed out after 1 minutes
aes_cipher_fi 62612933070112295805237113861233428439339355707306270963660031995434295896313 None
Job timed out after 1 minutes
aes_cipher_fi 29915184537686283085383969288709392069298922603256331739225499799669965232148 None
Job timed out after 1 minutes
UVM_FATAL (aes_base_vseq.sv:75) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 11233284034767436028596909398064916633874743645776451375782220183603806259072 242
UVM_FATAL @ 1252200315 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 1252200315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 72207659142493071289475708372965069909330422041480453046842718905620195462660 1185
UVM_FATAL @ 378596258 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 378596258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 31680705521457742810218683044601594680897919580265920293658902911062203564174 170
UVM_FATAL @ 73130090 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 73130090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1142): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS)
aes_fi 79160381691568893157657966653470033755578159479322486759175926738063046996207 2398
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1142): (time 6858591 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 6848591 PS)
UVM_ERROR @ 6858591 ps: (aes_core.sv:1142) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 6858591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_alert_reset 95246110810393990619345054916235194805818401556269672612320777494642384556194 2447
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1142): (time 7085657 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 7075556 PS)
UVM_ERROR @ 7085657 ps: (aes_core.sv:1142) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 7085657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 44830551062902915779602117026018974998369548062103971182681841723136098330383 143
UVM_FATAL @ 10005276810 ps: (aes_core_fi_vseq.sv:70) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10005276810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 54792450861301945928024303904356393902045818366477291516932153748545141335202 149
UVM_FATAL @ 10008547551 ps: (aes_core_fi_vseq.sv:70) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008547551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '*' in file '/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_*/aes_scoreboard.sv' at time * PS + *.
aes_fi 2524363479220528634541000579170039083892074629405372745909930111901336708393 4989
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '738' in file '/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 15607278 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '738' in file '/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 15607278 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '738' in file '/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 15607278 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '738' in file '/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 15607278 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '738' in file '/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 15607278 PS + 10.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
aes_core_fi 93519402675898181323734018011834083287021299331462440642783131516531599380912 143
UVM_FATAL @ 10123863514 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x1a7c8d84, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10123863514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:910) scoreboard [scoreboard]
aes_fi 103628857813122139977663414225855172377308122837928939877928920109987545761767 10501
UVM_FATAL @ 88867825 ps: (aes_scoreboard.sv:910) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 58940326583922442009071283567486287445203845979349702557699747365947753775547 145
UVM_FATAL @ 10046045332 ps: (aes_core_fi_vseq.sv:93) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10046045332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 65833861990079637496866384638578440308721419867141828236103862931198990930197 153
UVM_FATAL @ 10020340897 ps: (aes_core_fi_vseq.sv:93) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10020340897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 98101111562869081128077521660957288348256213491648880978276997355617830397836 149
UVM_FATAL @ 10035016728 ps: (aes_core_fi_vseq.sv:93) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10035016728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_manual_config_err_vseq.sv:71) virtual_sequencer [aes_manual_config_err_vseq] WAS ABLE TO TRIGGER OPERATION WITH ILLEGAL MODE
aes_man_cfg_err 56062146724560216986241334042744331167102940548054378649581675853706215655173 141
UVM_FATAL @ 18862745 ps: (aes_manual_config_err_vseq.sv:71) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_manual_config_err_vseq] WAS ABLE TO TRIGGER OPERATION WITH ILLEGAL MODE
UVM_INFO @ 18862745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 19895398309544986055782389921006321471672483483528141120374650737087445641104 147
UVM_FATAL @ 10007834119 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007834119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 106703682707774101310998300120696220414061376294944006048979108442924299422744 144
UVM_FATAL @ 10017340953 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10017340953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 77970429875331787258250533125648286220059930535469017642707884724192743209933 152
UVM_FATAL @ 10060203158 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10060203158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 2923551721331830071326546549012380105443829821174958161620010358961460279078 155
UVM_FATAL @ 10012526429 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10012526429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 58571943229075112138429034275552588042314976471289984120322230684772674530468 147
UVM_FATAL @ 10008317355 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008317355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 4514775350417168536908665790716565268265273920007567928252186085985568860300 155
UVM_FATAL @ 10010551171 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010551171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 37307135640268108523598106763481143029300683120413537990501215882844889078846 155
UVM_FATAL @ 10003239578 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10003239578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 109155917715163951479697499373233854830920703034566266131750016108352845862056 151
UVM_FATAL @ 10007286955 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007286955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 6210503767098635090708220099433561041092912966775595116047675591412195527377 155
UVM_FATAL @ 10019109155 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10019109155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 3459107808927526977003355032720658854402296271540406265372039169287172682516 151
UVM_FATAL @ 10013196196 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10013196196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 99291344408622680679409787658978528776329357257909686500495172400258734019186 144
UVM_FATAL @ 10035588543 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10035588543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 29314922044097447077973851227497539703559213516002544095476663169086506024744 141
UVM_FATAL @ 10014625407 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014625407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 114922958604239493871700970398097825935809048127632939901948337745066322113646 142
UVM_FATAL @ 10004579118 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10004579118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 27534548127992209819405955210903776814354245868531760156055058664579397386631 151
UVM_FATAL @ 10035881867 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10035881867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 76757030588293699996528505245462684504295174336044969364431283581947895380762 152
UVM_FATAL @ 10004946375 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10004946375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
aes_cipher_fi 114190099163668812075421838552366873940687650859263966608656423010654105461331 149
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---