Simulation Results: alert_handler

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.03 %
  • code
  • 98.90 %
  • assert
  • 98.88 %
  • func
  • 99.32 %
  • line
  • 99.99 %
  • branch
  • 99.99 %
  • cond
  • 97.44 %
  • toggle
  • 97.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.77%
V2S
99.55%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
alert_handler_smoke 72.340s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
alert_handler_csr_hw_reset 8.760s 0.000us 5 5 100.00
csr_rw 20 20 100.00
alert_handler_csr_rw 10.490s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
alert_handler_csr_bit_bash 313.990s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
alert_handler_csr_aliasing 262.050s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
alert_handler_csr_mem_rw_with_rand_reset 12.610s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
alert_handler_csr_rw 10.490s 0.000us 20 20 100.00
alert_handler_csr_aliasing 262.050s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 50 50 100.00
alert_handler_esc_alert_accum 243.440s 0.000us 50 50 100.00
esc_timeout 50 50 100.00
alert_handler_esc_intr_timeout 73.740s 0.000us 50 50 100.00
entropy 50 50 100.00
alert_handler_entropy 2860.150s 0.000us 50 50 100.00
sig_int_fail 49 50 98.00
alert_handler_sig_int_fail 70.510s 0.000us 49 50 98.00
clk_skew 50 50 100.00
alert_handler_smoke 72.340s 0.000us 50 50 100.00
random_alerts 50 50 100.00
alert_handler_random_alerts 72.980s 0.000us 50 50 100.00
random_classes 50 50 100.00
alert_handler_random_classes 73.440s 0.000us 50 50 100.00
ping_timeout 20 50 40.00
alert_handler_ping_timeout 584.320s 0.000us 20 50 40.00
lpg 99 100 99.00
alert_handler_lpg 2560.000s 0.000us 49 50 98.00
alert_handler_lpg_stub_clk 2803.360s 0.000us 50 50 100.00
stress_all 49 50 98.00
alert_handler_stress_all 3572.540s 0.000us 49 50 98.00
alert_handler_entropy_stress_test 20 20 100.00
alert_handler_entropy_stress 82.910s 0.000us 20 20 100.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 4.270s 0.000us 20 20 100.00
intr_test 50 50 100.00
alert_handler_intr_test 2.320s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
alert_handler_tl_errors 29.440s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
alert_handler_tl_errors 29.440s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
alert_handler_csr_hw_reset 8.760s 0.000us 5 5 100.00
alert_handler_csr_rw 10.490s 0.000us 20 20 100.00
alert_handler_csr_aliasing 262.050s 0.000us 5 5 100.00
alert_handler_same_csr_outstanding 45.050s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
alert_handler_csr_hw_reset 8.760s 0.000us 5 5 100.00
alert_handler_csr_rw 10.490s 0.000us 20 20 100.00
alert_handler_csr_aliasing 262.050s 0.000us 5 5 100.00
alert_handler_same_csr_outstanding 45.050s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
alert_handler_shadow_reg_errors 293.350s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
alert_handler_shadow_reg_errors 293.350s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
alert_handler_shadow_reg_errors 293.350s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
alert_handler_shadow_reg_errors 293.350s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
alert_handler_shadow_reg_errors_with_csr_rw 950.990s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
alert_handler_sec_cm 26.890s 0.000us 5 5 100.00
alert_handler_tl_intg_err 69.070s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
alert_handler_tl_intg_err 69.070s 0.000us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
alert_handler_shadow_reg_errors 293.350s 0.000us 20 20 100.00
sec_cm_ping_timer_config_regwen 50 50 100.00
alert_handler_smoke 72.340s 0.000us 50 50 100.00
sec_cm_alert_config_regwen 50 50 100.00
alert_handler_smoke 72.340s 0.000us 50 50 100.00
sec_cm_alert_loc_config_regwen 50 50 100.00
alert_handler_smoke 72.340s 0.000us 50 50 100.00
sec_cm_class_config_regwen 50 50 100.00
alert_handler_smoke 72.340s 0.000us 50 50 100.00
sec_cm_alert_intersig_diff 49 50 98.00
alert_handler_sig_int_fail 70.510s 0.000us 49 50 98.00
sec_cm_lpg_intersig_mubi 49 50 98.00
alert_handler_lpg 2560.000s 0.000us 49 50 98.00
sec_cm_esc_intersig_diff 49 50 98.00
alert_handler_sig_int_fail 70.510s 0.000us 49 50 98.00
sec_cm_alert_rx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 2860.150s 0.000us 50 50 100.00
sec_cm_esc_tx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 2860.150s 0.000us 50 50 100.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 26.890s 0.000us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 26.890s 0.000us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 26.890s 0.000us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 26.890s 0.000us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 26.890s 0.000us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 26.890s 0.000us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 26.890s 0.000us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 26.890s 0.000us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 26.890s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 50 60.00
alert_handler_stress_all_with_rand_reset 533.910s 0.000us 30 50 60.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 78851187367201841002881353705846886019225150095632772186277400614610208762700 80
UVM_ERROR @ 2362924048 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2362924048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 43299571834701951645237781513129772809191989889443153005274411142365377059691 80
UVM_ERROR @ 1116185574 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1116185574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 57525996288148527336176162618110544013578515935387881976310959957375625416356 80
UVM_ERROR @ 1258617430 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1258617430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 105597818135723211317889534789415394123253492101829844195498248658766654663371 83
UVM_ERROR @ 2569892423 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2569892423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 3886733859265482383965097960437247260366331412597190802317640693189075106025 80
UVM_ERROR @ 212053753 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 212053753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 113508751549279150087868988608845444861419444728867201877359588393982621371848 80
UVM_ERROR @ 217770790 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 217770790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 79625257565243189788454045067983522060152913992512676294884888572373606540479 80
UVM_ERROR @ 2331124198 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2331124198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 77141487823732863017955123719128288301850031250484902014630792487623713519744 106
UVM_ERROR @ 5077565229 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 5077565229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 75694830562089495527333046522273740084131628900962149850313760928844625604197 108
UVM_ERROR @ 4528235530 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 4528235530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 40714351992343529488119824179173341280016189631461231404105130815785368846648 87
UVM_ERROR @ 1461051970 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 1461051970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 64019821817967258019928281549777834723239838979074534374128434762475647862225 108
UVM_ERROR @ 7681512723 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 7681512723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 72490173576828076604000906875412482947137365372542077456664939070801677100084 108
UVM_ERROR @ 52314339441 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 52314339441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 61130019772409096176310168673507376509010884253532254364379175609884463065997 88
UVM_ERROR @ 1955263425 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 1955263425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 44747588204250895447551336813650185924001300523779994125753297749998711057586 93
UVM_ERROR @ 11042266233 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 11042266233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 30319928498693871990989743750208746223226121802729264368329376729320663459543 81
UVM_ERROR @ 834803963 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (4 [0x4] vs 0 [0x0]) reg name: intr_state
UVM_INFO @ 834803963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 46706544071541828071173891386939847260198114402803316155001803964661884055946 102
UVM_ERROR @ 8660673981 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 8660673981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 64034453407315271098303450016642900767190143678968113798604347476487353046626 114
UVM_ERROR @ 10664728586 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 10664728586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 25603901074711308229517117986698857802097489141578934360389428087578470217287 129
UVM_ERROR @ 6929951908 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 6929951908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 55443602482235925462161543394865537381538305640143167288948065945232858565184 87
UVM_ERROR @ 775070277 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 775070277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 80693546823291261639878064466053432223440871473379655021284638478934194249336 99
UVM_ERROR @ 4090383804 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 4090383804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 97739028548564310819131095803906955635228527038471143081659085775893704162831 124
UVM_ERROR @ 34721502196 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 34721502196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 100463375327957920928523042074675168268598646956206141804907995127363381862725 84
UVM_ERROR @ 634929300 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 634929300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 114680435747326742940702249594989167023284277477448083958786934723884575797956 123
UVM_ERROR @ 6845519704 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 6845519704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 16048768320595171635665566987703301197888520186096430616165903836633414106666 132
UVM_ERROR @ 48818389855 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 48818389855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 90248518329704818058187118168956816101889986208709108650368446917210543047873 120
UVM_ERROR @ 23910725653 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 23910725653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 75171252225567051030049154428853890373397979469781341032345054372251394864279 126
UVM_ERROR @ 73461343469 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 73461343469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 83324350660127680067993154701373386033883713000984674178723902446356763213437 120
UVM_ERROR @ 7485672375 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 7485672375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 23570348614461183982530482587318111595463451623243874814135861105901867061498 84
UVM_ERROR @ 2870045950 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 2870045950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 73907608108758042277882068162577607274641805583820370159668182645190579907798 91
UVM_ERROR @ 734117675 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 734117675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 95387435220884867556795991861577441815372779819982917806283763998507604991824 105
UVM_ERROR @ 33826587175 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 33826587175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 54687590683537809186171831555061557459993436335597758183878377029569637691599 143
UVM_ERROR @ 11976099244 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11976099244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 63518932583104105253018351672754728206420276784033052620032021149925453228267 93
UVM_ERROR @ 635612752 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 635612752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 4995344309810708371895069375396831775274919574450362822108032259404146411600 96
UVM_ERROR @ 1335504257 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1335504257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 59127688327859774794875122065830581535542067109142536439420544795953323924911 176
UVM_ERROR @ 5490430694 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5490430694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 67230101932856857037525998407900593568898496003009268518647430557176101973441 148
UVM_ERROR @ 10644531588 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10644531588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 22073092834369259413767315169015430036733030379450649741258114053686386891826 138
UVM_ERROR @ 2304367045 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2304367045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 83949867229896293840739212905377137506765843371114755373625876478418513968733 112
UVM_ERROR @ 1301292640 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1301292640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 44186328905748365611467600595079226977115120252432302770570375937976591266824 157
UVM_ERROR @ 8519262970 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8519262970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 65803040466777191565123272670752264118941358443302365010272908343215844307972 97
UVM_ERROR @ 2520883486 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2520883486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 31658054517414994902350995715979883039030914572841334016819742832012954979553 132
UVM_ERROR @ 1666583596 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1666583596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 69306872362764161980426129401176624932823942388554533615284352325664137018819 98
UVM_ERROR @ 8362529860 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8362529860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 55341751159417445138450762474498167460857554701183066656166440979378772177880 101
UVM_ERROR @ 5726162193 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5726162193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 63648623069951664820040158230169599132356078319790111815408989657012332782677 210
UVM_ERROR @ 12882985638 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12882985638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 85287888843829963568257216887616374342196821831078763136622408495855588409058 169
UVM_ERROR @ 9869933263 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9869933263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 96823115765427084143478066266574693531583194803068313328418586481843272225091 93
UVM_ERROR @ 904174721 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 904174721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 94144819836528945463001745241169855008123455066142872701901683573556056202312 138
UVM_ERROR @ 3271785575 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3271785575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 24395837162229800434541281924004333714415468439791157190372621151255953142681 84
UVM_ERROR @ 216768738 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 216768738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
alert_handler_stress_all_with_rand_reset 11662266968134896844761348251854395631381648612224164843854454886813937535414 133
UVM_ERROR @ 1929040442 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1929040442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 112836440165935492172349801462859836034058615988653176351291547278925975325397 199
UVM_ERROR @ 22285257712 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 22285257712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 75834733331136076625373392719554686321707379945485755908995375059806418561591 98
UVM_ERROR @ 1705672281 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1705672281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:487) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt
alert_handler_sig_int_fail 89298002026712352217650669487336859246122573216748062504530522790355591192643 85
UVM_ERROR @ 357066545 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (127 [0x7f] vs 128 [0x80]) reg name: alert_handler_reg_block.classa_accum_cnt
UVM_INFO @ 357066545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscPingFail
alert_handler_ping_timeout 25736246341634634343473231493858030082815343984922087088214678493327078539796 84
UVM_ERROR @ 158290786 ps: (alert_handler_scoreboard.sv:258) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscPingFail
UVM_INFO @ 158290786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:487) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_accum_cnt
alert_handler_stress_all 89514848420210369356440306148993232685515764499016559554004487350784923666473 137
UVM_ERROR @ 28169560631 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1571 [0x623] vs 1572 [0x624]) reg name: alert_handler_reg_block.classc_accum_cnt
UVM_INFO @ 28169560631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---