Simulation Results: chip

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.54 %
  • code
  • 86.39 %
  • assert
  • 97.87 %
  • func
  • 99.35 %
  • line
  • 94.90 %
  • branch
  • 94.93 %
  • cond
  • 93.25 %
  • toggle
  • 91.74 %
  • FSM
  • 57.14 %
Validation stages
V1
94.53%
V2
90.95%
V2S
66.67%
V3
78.79%
unmapped
81.82%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 12 12 100.00
chip_sw_example_flash 231.400s 0.000us 3 3 100.00
chip_sw_example_rom 104.910s 0.000us 3 3 100.00
chip_sw_example_manufacturer 230.790s 0.000us 3 3 100.00
chip_sw_example_concurrency 214.700s 0.000us 3 3 100.00
csr_hw_reset 5 5 100.00
chip_csr_hw_reset 351.210s 0.000us 5 5 100.00
csr_rw 20 20 100.00
chip_csr_rw 654.510s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
chip_csr_bit_bash 5447.140s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
chip_csr_aliasing 5972.810s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 6 20 30.00
chip_csr_mem_rw_with_rand_reset 858.110s 0.000us 6 20 30.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
chip_csr_aliasing 5972.810s 0.000us 5 5 100.00
chip_csr_rw 654.510s 0.000us 20 20 100.00
xbar_smoke 100 100 100.00
xbar_smoke 11.240s 0.000us 100 100 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 367.750s 0.000us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 367.750s 0.000us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 367.750s 0.000us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 512.410s 0.000us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 512.410s 0.000us 5 5 100.00
chip_sw_uart_tx_rx_idx1 528.530s 0.000us 5 5 100.00
chip_sw_uart_tx_rx_idx2 580.390s 0.000us 5 5 100.00
chip_sw_uart_tx_rx_idx3 452.090s 0.000us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 2186.460s 0.000us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1373.520s 0.000us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1534.040s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 10 10 100.00
chip_padctrl_attributes 266.700s 0.000us 10 10 100.00
chip_padctrl_attributes 10 10 100.00
chip_padctrl_attributes 266.700s 0.000us 10 10 100.00
chip_sw_sleep_pin_mio_dio_val 3 3 100.00
chip_sw_sleep_pin_mio_dio_val 233.130s 0.000us 3 3 100.00
chip_sw_sleep_pin_wake 3 3 100.00
chip_sw_sleep_pin_wake 317.580s 0.000us 3 3 100.00
chip_sw_sleep_pin_retention 3 3 100.00
chip_sw_sleep_pin_retention 278.610s 0.000us 3 3 100.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1263.420s 0.000us 5 5 100.00
chip_tap_straps_testunlock0 341.300s 0.000us 5 5 100.00
chip_tap_straps_rma 760.900s 0.000us 5 5 100.00
chip_tap_straps_prod 873.760s 0.000us 5 5 100.00
chip_sw_pattgen_ios 3 3 100.00
chip_sw_pattgen_ios 277.390s 0.000us 3 3 100.00
chip_sw_sleep_pwm_pulses 3 3 100.00
chip_sw_sleep_pwm_pulses 1081.520s 0.000us 3 3 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 603.940s 0.000us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 603.940s 0.000us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 892.960s 0.000us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 2265.030s 0.000us 0 3 0.00
chip_sw_ast_sys_clk_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 508.800s 0.000us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 840.150s 0.000us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4668.670s 0.000us 3 3 100.00
chip_sw_aes_enc_jitter_en 274.840s 0.000us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1046.670s 0.000us 3 3 100.00
chip_sw_hmac_enc_jitter_en 201.490s 0.000us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1950.200s 0.000us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 247.800s 0.000us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 502.450s 0.000us 3 3 100.00
chip_sw_clkmgr_jitter 240.820s 0.000us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 188.220s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 8 8 100.00
chip_sw_sensor_ctrl_alert 899.740s 0.000us 5 5 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 302.620s 0.000us 3 3 100.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 279.120s 0.000us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 302.620s 0.000us 3 3 100.00
chip_sw_smoketest 51 51 100.00
chip_sw_flash_scrambling_smoketest 212.520s 0.000us 3 3 100.00
chip_sw_aes_smoketest 265.170s 0.000us 3 3 100.00
chip_sw_aon_timer_smoketest 261.470s 0.000us 3 3 100.00
chip_sw_clkmgr_smoketest 173.200s 0.000us 3 3 100.00
chip_sw_csrng_smoketest 184.600s 0.000us 3 3 100.00
chip_sw_entropy_src_smoketest 1121.600s 0.000us 3 3 100.00
chip_sw_gpio_smoketest 267.910s 0.000us 3 3 100.00
chip_sw_hmac_smoketest 279.230s 0.000us 3 3 100.00
chip_sw_kmac_smoketest 271.840s 0.000us 3 3 100.00
chip_sw_otbn_smoketest 1253.600s 0.000us 3 3 100.00
chip_sw_pwrmgr_smoketest 449.610s 0.000us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 341.180s 0.000us 3 3 100.00
chip_sw_rv_plic_smoketest 242.540s 0.000us 3 3 100.00
chip_sw_rv_timer_smoketest 245.000s 0.000us 3 3 100.00
chip_sw_rstmgr_smoketest 213.170s 0.000us 3 3 100.00
chip_sw_sram_ctrl_smoketest 213.610s 0.000us 3 3 100.00
chip_sw_uart_smoketest 230.200s 0.000us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 220.350s 0.000us 3 3 100.00
chip_sw_rom_functests 0 3 0.00
rom_keymgr_functest 507.260s 0.000us 0 3 0.00
chip_sw_boot 3 3 100.00
chip_sw_uart_tx_rx_bootstrap 12727.370s 0.000us 3 3 100.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 3750.130s 0.000us 3 3 100.00
chip_sw_rom_raw_unlock 2 3 66.67
rom_raw_unlock 1095.240s 0.000us 2 3 66.67
chip_sw_power_idle_load 0 3 0.00
chip_sw_power_idle_load 289.970s 0.000us 0 3 0.00
chip_sw_power_sleep_load 0 3 0.00
chip_sw_power_sleep_load 268.160s 0.000us 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 3 3 100.00
chip_sw_exit_test_unlocked_bootstrap 10810.360s 0.000us 3 3 100.00
chip_sw_inject_scramble_seed 3 3 100.00
chip_sw_inject_scramble_seed 11636.860s 0.000us 3 3 100.00
tl_d_oob_addr_access 4 30 13.33
chip_tl_errors 244.670s 0.000us 4 30 13.33
tl_d_illegal_access 4 30 13.33
chip_tl_errors 244.670s 0.000us 4 30 13.33
tl_d_outstanding_access 50 50 100.00
chip_csr_aliasing 5972.810s 0.000us 5 5 100.00
chip_same_csr_outstanding 4054.740s 0.000us 20 20 100.00
chip_csr_hw_reset 351.210s 0.000us 5 5 100.00
chip_csr_rw 654.510s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
chip_csr_aliasing 5972.810s 0.000us 5 5 100.00
chip_same_csr_outstanding 4054.740s 0.000us 20 20 100.00
chip_csr_hw_reset 351.210s 0.000us 5 5 100.00
chip_csr_rw 654.510s 0.000us 20 20 100.00
xbar_base_random_sequence 100 100 100.00
xbar_random 84.790s 0.000us 100 100 100.00
xbar_random_delay 600 600 100.00
xbar_smoke_zero_delays 7.880s 0.000us 100 100 100.00
xbar_smoke_large_delays 107.630s 0.000us 100 100 100.00
xbar_smoke_slow_rsp 95.060s 0.000us 100 100 100.00
xbar_random_zero_delays 46.350s 0.000us 100 100 100.00
xbar_random_large_delays 489.730s 0.000us 100 100 100.00
xbar_random_slow_rsp 424.160s 0.000us 100 100 100.00
xbar_unmapped_address 200 200 100.00
xbar_unmapped_addr 49.930s 0.000us 100 100 100.00
xbar_error_and_unmapped_addr 55.330s 0.000us 100 100 100.00
xbar_error_cases 200 200 100.00
xbar_error_random 82.070s 0.000us 100 100 100.00
xbar_error_and_unmapped_addr 55.330s 0.000us 100 100 100.00
xbar_all_access_same_device 200 200 100.00
xbar_access_same_device 129.650s 0.000us 100 100 100.00
xbar_access_same_device_slow_rsp 876.350s 0.000us 100 100 100.00
xbar_all_hosts_use_same_source_id 100 100 100.00
xbar_same_source 78.120s 0.000us 100 100 100.00
xbar_stress_all 200 200 100.00
xbar_stress_all 598.500s 0.000us 100 100 100.00
xbar_stress_all_with_error 582.180s 0.000us 100 100 100.00
xbar_stress_with_reset 200 200 100.00
xbar_stress_all_with_rand_reset 556.330s 0.000us 100 100 100.00
xbar_stress_all_with_reset_error 806.580s 0.000us 100 100 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 3750.130s 0.000us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 3404.340s 0.000us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 3544.540s 0.000us 3 3 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2903.180s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3857.640s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3818.620s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3952.310s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3670.250s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 19.670s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 19.100s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 19.890s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 21.290s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 23.910s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 24.130s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 20.840s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 29.740s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 18.050s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 22.230s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 21.870s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 19.680s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 23.090s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 25.180s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 24.590s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 26.490s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 22.830s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 29.250s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 22.210s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 21.660s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 20.330s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 19.060s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17.400s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 26.490s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 19.390s 0.000us 0 1 0.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 2911.690s 0.000us 3 3 100.00
rom_e2e_asm_init_dev 3889.200s 0.000us 3 3 100.00
rom_e2e_asm_init_prod 3764.100s 0.000us 3 3 100.00
rom_e2e_asm_init_prod_end 4080.300s 0.000us 3 3 100.00
rom_e2e_asm_init_rma 3938.380s 0.000us 3 3 100.00
rom_e2e_keymgr_init 8 9 88.89
rom_e2e_keymgr_init_rom_ext_meas 7572.880s 0.000us 2 3 66.67
rom_e2e_keymgr_init_rom_ext_no_meas 7638.890s 0.000us 3 3 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 7465.600s 0.000us 3 3 100.00
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 4070.280s 0.000us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0.000s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0.000s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 281.950s 0.000us 3 3 100.00
chip_sw_aes_enc_jitter_en 274.840s 0.000us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 218.910s 0.000us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 213.890s 0.000us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_sideload_aes 2227.030s 0.000us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 227.840s 0.000us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 538.260s 0.000us 3 3 100.00
chip_sw_all_escalation_resets 87 100 87.00
chip_sw_all_escalation_resets 648.610s 0.000us 87 100 87.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 727.860s 0.000us 3 3 100.00
chip_plic_all_irqs_10 385.320s 0.000us 3 3 100.00
chip_plic_all_irqs_20 450.390s 0.000us 3 3 100.00
chip_sw_alert_handler_entropy 3 3 100.00
chip_sw_alert_handler_entropy 342.110s 0.000us 3 3 100.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 1505.630s 0.000us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 422.360s 0.000us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 259.570s 0.000us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1312.030s 0.000us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1293.500s 0.000us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1059.730s 0.000us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 12557.650s 0.000us 3 3 100.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 345.430s 0.000us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 449.610s 0.000us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 345.430s 0.000us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 2 3 66.67
chip_sw_aon_timer_wdog_bite_reset 722.270s 0.000us 2 3 66.67
chip_sw_aon_timer_sleep_wdog_bite_reset 2 3 66.67
chip_sw_aon_timer_wdog_bite_reset 722.270s 0.000us 2 3 66.67
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 547.590s 0.000us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 423.560s 0.000us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 793.430s 0.000us 3 3 100.00
chip_sw_aes_idle 213.890s 0.000us 3 3 100.00
chip_sw_hmac_enc_idle 259.240s 0.000us 3 3 100.00
chip_sw_kmac_idle 168.320s 0.000us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 387.210s 0.000us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 458.270s 0.000us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 464.220s 0.000us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 376.920s 0.000us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1219.070s 0.000us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 535.890s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 537.820s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 487.320s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 480.580s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 554.420s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 514.500s 0.000us 3 3 100.00
chip_sw_ast_clk_outputs 892.960s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 831.600s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 487.320s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 480.580s 0.000us 3 3 100.00
chip_sw_clkmgr_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 508.800s 0.000us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 840.150s 0.000us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4668.670s 0.000us 3 3 100.00
chip_sw_aes_enc_jitter_en 274.840s 0.000us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1046.670s 0.000us 3 3 100.00
chip_sw_hmac_enc_jitter_en 201.490s 0.000us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1950.200s 0.000us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 247.800s 0.000us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 502.450s 0.000us 3 3 100.00
chip_sw_clkmgr_jitter 240.820s 0.000us 3 3 100.00
chip_sw_clkmgr_extended_range 33 33 100.00
chip_sw_clkmgr_jitter_reduced_freq 218.900s 0.000us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 550.950s 0.000us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 845.540s 0.000us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4793.990s 0.000us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 225.560s 0.000us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 246.360s 0.000us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1559.770s 0.000us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 242.080s 0.000us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 495.200s 0.000us 3 3 100.00
chip_sw_flash_init_reduced_freq 1486.900s 0.000us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 10947.280s 0.000us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 892.960s 0.000us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 3 3 100.00
chip_sw_clkmgr_sleep_frequency 462.240s 0.000us 3 3 100.00
chip_sw_clkmgr_reset_frequency 3 3 100.00
chip_sw_clkmgr_reset_frequency 370.490s 0.000us 3 3 100.00
chip_sw_clkmgr_escalation_reset 87 100 87.00
chip_sw_all_escalation_resets 648.610s 0.000us 87 100 87.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1312.030s 0.000us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 1409.900s 0.000us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 3 33.33
chip_sw_csrng_fuse_en_sw_app_read_test 306.350s 0.000us 1 3 33.33
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 616.860s 0.000us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 246.900s 0.000us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 8701.490s 0.000us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 174.740s 0.000us 3 3 100.00
chip_sw_edn_entropy_reqs 1135.130s 0.000us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 174.740s 0.000us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 1409.900s 0.000us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 235.480s 0.000us 3 3 100.00
chip_sw_flash_init 3 3 100.00
chip_sw_flash_init 1940.200s 0.000us 3 3 100.00
chip_sw_flash_host_access 6 6 100.00
chip_sw_flash_ctrl_access 774.610s 0.000us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 840.150s 0.000us 3 3 100.00
chip_sw_flash_ctrl_ops 6 6 100.00
chip_sw_flash_ctrl_ops 433.810s 0.000us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en 508.800s 0.000us 3 3 100.00
chip_sw_flash_rma_unlocked 3 3 100.00
chip_sw_flash_rma_unlocked 4939.600s 0.000us 3 3 100.00
chip_sw_flash_scramble 3 3 100.00
chip_sw_flash_init 1940.200s 0.000us 3 3 100.00
chip_sw_flash_idle_low_power 3 3 100.00
chip_sw_flash_ctrl_idle_low_power 319.910s 0.000us 3 3 100.00
chip_sw_flash_keymgr_seeds 3 3 100.00
chip_sw_keymgr_key_derivation 2012.710s 0.000us 3 3 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 247.980s 0.000us 0 3 0.00
chip_sw_flash_creator_seed_wipe_on_rma 3 3 100.00
chip_sw_flash_rma_unlocked 4939.600s 0.000us 3 3 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 247.980s 0.000us 0 3 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 247.980s 0.000us 0 3 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 247.980s 0.000us 0 3 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 247.980s 0.000us 0 3 0.00
chip_sw_flash_lc_escalate_en 87 100 87.00
chip_sw_all_escalation_resets 648.610s 0.000us 87 100 87.00
chip_sw_flash_prim_tl_access 3 3 100.00
chip_prim_tl_access 593.020s 0.000us 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 740.290s 0.000us 3 3 100.00
chip_sw_flash_ctrl_escalation_reset 3 3 100.00
chip_sw_flash_crash_alert 488.850s 0.000us 3 3 100.00
chip_sw_flash_ctrl_write_clear 3 3 100.00
chip_sw_flash_crash_alert 488.850s 0.000us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 259.850s 0.000us 3 3 100.00
chip_sw_hmac_enc_jitter_en 201.490s 0.000us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 259.240s 0.000us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 977.780s 0.000us 3 3 100.00
chip_sw_hmac_multistream_mode 3 3 100.00
chip_sw_hmac_multistream 1024.290s 0.000us 3 3 100.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 564.240s 0.000us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 573.500s 0.000us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 512.310s 0.000us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 465.120s 0.000us 3 3 100.00
chip_sw_keymgr_key_derivation 6 6 100.00
chip_sw_keymgr_key_derivation 2012.710s 0.000us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1950.200s 0.000us 3 3 100.00
chip_sw_keymgr_sideload_kmac 3 3 100.00
chip_sw_keymgr_sideload_kmac 2213.410s 0.000us 3 3 100.00
chip_sw_keymgr_sideload_aes 3 3 100.00
chip_sw_keymgr_sideload_aes 2227.030s 0.000us 3 3 100.00
chip_sw_keymgr_sideload_otbn 3 3 100.00
chip_sw_keymgr_sideload_otbn 3919.340s 0.000us 3 3 100.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 199.540s 0.000us 3 3 100.00
chip_sw_kmac_mode_kmac 261.820s 0.000us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 247.800s 0.000us 3 3 100.00
chip_sw_kmac_app_keymgr 3 3 100.00
chip_sw_keymgr_key_derivation 2012.710s 0.000us 3 3 100.00
chip_sw_kmac_app_lc 15 15 100.00
chip_sw_lc_ctrl_transition 1152.300s 0.000us 15 15 100.00
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 237.070s 0.000us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 2112.280s 0.000us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 168.320s 0.000us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 538.260s 0.000us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1263.420s 0.000us 5 5 100.00
chip_tap_straps_rma 760.900s 0.000us 5 5 100.00
chip_tap_straps_prod 873.760s 0.000us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 179.300s 0.000us 3 3 100.00
chip_sw_lc_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 1152.300s 0.000us 15 15 100.00
chip_sw_lc_ctrl_transitions 15 15 100.00
chip_sw_lc_ctrl_transition 1152.300s 0.000us 15 15 100.00
chip_sw_lc_ctrl_kmac_req 15 15 100.00
chip_sw_lc_ctrl_transition 1152.300s 0.000us 15 15 100.00
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_key_derivation_prod 2012.310s 0.000us 3 3 100.00
chip_sw_lc_ctrl_broadcast 76 84 90.48
chip_prim_tl_access 593.020s 0.000us 3 3 100.00
chip_rv_dm_lc_disabled 399.570s 0.000us 1 3 33.33
chip_sw_flash_ctrl_lc_rw_en 247.980s 0.000us 0 3 0.00
chip_sw_flash_rma_unlocked 4939.600s 0.000us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 352.500s 0.000us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 669.510s 0.000us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 591.000s 0.000us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 627.110s 0.000us 0 3 0.00
chip_sw_lc_ctrl_transition 1152.300s 0.000us 15 15 100.00
chip_sw_keymgr_key_derivation 2012.710s 0.000us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 572.760s 0.000us 3 3 100.00
chip_sw_sram_ctrl_execution_main 741.560s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 831.600s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 535.890s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 537.820s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 487.320s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 480.580s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 554.420s 0.000us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 514.500s 0.000us 3 3 100.00
chip_tap_straps_dev 1263.420s 0.000us 5 5 100.00
chip_tap_straps_rma 760.900s 0.000us 5 5 100.00
chip_tap_straps_prod 873.760s 0.000us 5 5 100.00
chip_lc_scrap 6 6 100.00
chip_sw_lc_ctrl_rma_to_scrap 231.770s 0.000us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 128.920s 0.000us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 114.550s 0.000us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 271.600s 0.000us 3 3 100.00
chip_lc_test_locked 4 6 66.67
chip_rv_dm_lc_disabled 399.570s 0.000us 1 3 33.33
chip_sw_lc_walkthrough_testunlocks 2246.100s 0.000us 3 3 100.00
chip_sw_lc_walkthrough 6 15 40.00
chip_sw_lc_walkthrough_dev 919.770s 0.000us 0 3 0.00
chip_sw_lc_walkthrough_prod 909.510s 0.000us 0 3 0.00
chip_sw_lc_walkthrough_prodend 860.450s 0.000us 3 3 100.00
chip_sw_lc_walkthrough_rma 501.640s 0.000us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 2246.100s 0.000us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 9 9 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 113.890s 0.000us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 123.250s 0.000us 3 3 100.00
rom_volatile_raw_unlock 97.930s 0.000us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 4495.760s 0.000us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4668.670s 0.000us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 793.430s 0.000us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 793.430s 0.000us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 793.430s 0.000us 3 3 100.00
chip_sw_otbn_mem_scramble 2 3 66.67
chip_sw_otbn_mem_scramble 377.910s 0.000us 2 3 66.67
chip_otp_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 1152.300s 0.000us 15 15 100.00
chip_sw_otp_ctrl_keys 14 15 93.33
chip_sw_flash_init 1940.200s 0.000us 3 3 100.00
chip_sw_otbn_mem_scramble 377.910s 0.000us 2 3 66.67
chip_sw_keymgr_key_derivation 2012.710s 0.000us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 559.100s 0.000us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 224.060s 0.000us 3 3 100.00
chip_sw_otp_ctrl_entropy 14 15 93.33
chip_sw_flash_init 1940.200s 0.000us 3 3 100.00
chip_sw_otbn_mem_scramble 377.910s 0.000us 2 3 66.67
chip_sw_keymgr_key_derivation 2012.710s 0.000us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 559.100s 0.000us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 224.060s 0.000us 3 3 100.00
chip_sw_otp_ctrl_program 15 15 100.00
chip_sw_lc_ctrl_transition 1152.300s 0.000us 15 15 100.00
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 536.850s 0.000us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 179.300s 0.000us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 27 30 90.00
chip_prim_tl_access 593.020s 0.000us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 352.500s 0.000us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 669.510s 0.000us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 591.000s 0.000us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 627.110s 0.000us 0 3 0.00
chip_sw_lc_ctrl_transition 1152.300s 0.000us 15 15 100.00
chip_sw_otp_prim_tl_access 3 3 100.00
chip_prim_tl_access 593.020s 0.000us 3 3 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1009.550s 0.000us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 434.330s 0.000us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1181.650s 0.000us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 341.090s 0.000us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 3 33.33
chip_sw_pwrmgr_deep_sleep_por_reset 529.150s 0.000us 1 3 33.33
chip_sw_pwrmgr_normal_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 638.360s 0.000us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1453.660s 0.000us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 3 6 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1032.000s 0.000us 1 3 33.33
chip_sw_aon_timer_wdog_bite_reset 722.270s 0.000us 2 3 66.67
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 2 3 66.67
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1207.270s 0.000us 2 3 66.67
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 557.830s 0.000us 3 3 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 434.330s 0.000us 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 410.510s 0.000us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 3 33.33
chip_sw_pwrmgr_random_sleep_power_glitch_reset 3104.860s 0.000us 1 3 33.33
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 454.150s 0.000us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 416.490s 0.000us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 3 33.33
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1712.750s 0.000us 1 3 33.33
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 933.930s 0.000us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1411.390s 0.000us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2676.440s 0.000us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 217.960s 0.000us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 87 100 87.00
chip_sw_all_escalation_resets 648.610s 0.000us 87 100 87.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 572.760s 0.000us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 572.760s 0.000us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 10 12 83.33
chip_sw_pwrmgr_all_reset_reqs 1411.390s 0.000us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1712.750s 0.000us 1 3 33.33
chip_sw_pwrmgr_wdog_reset 557.830s 0.000us 3 3 100.00
chip_sw_pwrmgr_smoketest 449.610s 0.000us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 360.680s 0.000us 3 3 100.00
chip_sw_rstmgr_cpu_info 0 3 0.00
chip_sw_rstmgr_cpu_info 422.280s 0.000us 0 3 0.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 372.620s 0.000us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 1505.630s 0.000us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 203.270s 0.000us 3 3 100.00
chip_sw_rstmgr_escalation_reset 87 100 87.00
chip_sw_all_escalation_resets 648.610s 0.000us 87 100 87.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1293.500s 0.000us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 644.850s 0.000us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 656.020s 0.000us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 297.340s 0.000us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 224.060s 0.000us 3 3 100.00
chip_sw_rv_core_ibex_fault_dump 0 3 0.00
chip_sw_rstmgr_cpu_info 422.280s 0.000us 0 3 0.00
chip_sw_rv_core_ibex_double_fault 0 3 0.00
chip_sw_rstmgr_cpu_info 422.280s 0.000us 0 3 0.00
chip_jtag_csr_rw 3 3 100.00
chip_jtag_csr_rw 1732.990s 0.000us 3 3 100.00
chip_jtag_mem_access 3 3 100.00
chip_jtag_mem_access 1372.620s 0.000us 3 3 100.00
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 360.680s 0.000us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 256.520s 0.000us 0 3 0.00
chip_rv_dm_access_after_wakeup 3 3 100.00
chip_sw_rv_dm_access_after_wakeup 442.910s 0.000us 3 3 100.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 760.900s 0.000us 5 5 100.00
chip_rv_dm_lc_disabled 1 3 33.33
chip_rv_dm_lc_disabled 399.570s 0.000us 1 3 33.33
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 727.860s 0.000us 3 3 100.00
chip_plic_all_irqs_10 385.320s 0.000us 3 3 100.00
chip_plic_all_irqs_20 450.390s 0.000us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 244.160s 0.000us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 222.530s 0.000us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 3750.130s 0.000us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 735.270s 0.000us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 289.150s 0.000us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 326.420s 0.000us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 306.080s 0.000us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 559.100s 0.000us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 502.450s 0.000us 3 3 100.00
chip_sw_sleep_sram_ret_contents 6 6 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 684.730s 0.000us 3 3 100.00
chip_sw_sleep_sram_ret_contents_scramble 628.690s 0.000us 3 3 100.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 741.560s 0.000us 3 3 100.00
chip_sw_sram_lc_escalation 93 106 87.74
chip_sw_all_escalation_resets 648.610s 0.000us 87 100 87.00
chip_sw_data_integrity_escalation 603.940s 0.000us 6 6 100.00
chip_sw_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 933.930s 0.000us 3 3 100.00
chip_sw_sysrst_ctrl_reset 1476.570s 0.000us 3 3 100.00
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 257.800s 0.000us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 296.790s 0.000us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 458.070s 0.000us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 3 3 100.00
chip_sw_sysrst_ctrl_reset 1476.570s 0.000us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_reset 3 3 100.00
chip_sw_sysrst_ctrl_reset 1476.570s 0.000us 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3286.320s 0.000us 3 3 100.00
chip_sw_sysrst_ctrl_flash_wp_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3286.320s 0.000us 3 3 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 456.520s 0.000us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0.000s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 194.750s 0.000us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 209.990s 0.000us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 417.750s 0.000us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 389.240s 0.000us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1275.000s 0.000us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6372.390s 0.000us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2449.020s 0.000us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 210.290s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 263.270s 0.000us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 3 33.33
chip_sw_rv_core_ibex_lockstep_glitch 140.060s 0.000us 1 3 33.33
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 15395.930s 0.000us 1 1 100.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 1386.440s 0.000us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 519.700s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 193.410s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 185.750s 0.000us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 75.530s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 88.690s 0.000us 0 1 0.00
rom_e2e_jtag_inject_rma 98.370s 0.000us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 11.490s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 3 0.00
chip_sw_clkmgr_jitter_frequency 403.290s 0.000us 0 3 0.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 427.650s 0.000us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1180.020s 0.000us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 1587.930s 0.000us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 345.270s 0.000us 3 3 100.00
chip_sw_flash_memory_protection 3 3 100.00
chip_sw_flash_ctrl_mem_protection 833.560s 0.000us 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 211.470s 0.000us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 264.800s 0.000us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 3 3 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 397.090s 0.000us 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 406.020s 0.000us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1411.390s 0.000us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 519.700s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 193.410s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 185.750s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 3 3 100.00
chip_sw_rv_dm_access_after_escalation_reset 476.090s 0.000us 3 3 100.00
chip_sw_plic_alerts 87 100 87.00
chip_sw_all_escalation_resets 648.610s 0.000us 87 100 87.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 0.000s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 0.000s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 3 3 100.00
chip_sw_spi_device_pinmux_sleep_retention 269.700s 0.000us 3 3 100.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 512.410s 0.000us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3812.290s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 18 22 81.82
chip_sival_flash_info_access 302.210s 0.000us 3 3 100.00
chip_sw_rstmgr_rst_cnsty_escalation 515.610s 0.000us 3 3 100.00
chip_sw_otp_ctrl_rot_auth_config 6.150s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 234.780s 0.000us 3 3 100.00
chip_sw_otp_ctrl_descrambling 247.300s 0.000us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 394.290s 0.000us 3 3 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 12.056s 0.000us 0 3 0.00
chip_sw_flash_ctrl_write_clear 242.600s 0.000us 3 3 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 7115126542366862764288453222383785529438845438261146001539173694330042414451 217
UVM_ERROR @ 2532.834500 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@39651) { a_addr: 'h10620 a_data: 'hc30b8a83 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h19 a_opcode: 'h4 a_user: 'h18653 d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2532.834500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 88362668128149231038628380128754720093387736668168717918065372420063607712467 224
UVM_ERROR @ 1701.073898 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31569) { a_addr: 'h106bc a_data: 'h2bd943b9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h18a1b d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1701.073898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 51668611013414622412806714556478892585474212986074810325888003850667151709742 217
UVM_ERROR @ 2082.578909 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@38621) { a_addr: 'h106fc a_data: 'h2bec8353 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h1a296 d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2082.578909 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 60360181749297258520669830146413033914242206912945396068195983054894525357260 217
UVM_ERROR @ 2790.223580 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@33597) { a_addr: 'h1050c a_data: 'ha28f399b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3d a_opcode: 'h4 a_user: 'h18ae3 d_param: 'h0 d_source: 'h3d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2790.223580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 33691186157210855120983519813491265719873574587123966788995907115002100925477 224
UVM_ERROR @ 2625.241832 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32049) { a_addr: 'h105e8 a_data: 'h1d7795a5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h20 a_opcode: 'h4 a_user: 'h186fc d_param: 'h0 d_source: 'h20 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2625.241832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 14864102039435760076070397822751765412917691473676387201545706931979145047619 217
UVM_ERROR @ 3080.124528 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32685) { a_addr: 'h10648 a_data: 'h2034155a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h1a2e3 d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3080.124528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 88686036757999979234975469633620886264635197009070627600466232030179705481176 242
UVM_ERROR @ 6434.896100 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@215447) { a_addr: 'h106a0 a_data: 'h1db5946a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h1b68e d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 6434.896100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 56386714098369587896163229855392619463386504022292550061830415098021948707840 217
UVM_ERROR @ 2724.344460 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31681) { a_addr: 'h10610 a_data: 'h8b8c7f8b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h1ba10 d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2724.344460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 6984188162304087276740824227592909070812807950276442263758045764718374008121 224
UVM_ERROR @ 2752.014536 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32599) { a_addr: 'h10348 a_data: 'hefee445f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1b6f4 d_param: 'h0 d_source: 'h29 d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2752.014536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 100801810351302989654189775885982379048283962051638729548777040137826781907652 224
UVM_ERROR @ 2128.316325 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31485) { a_addr: 'h104f4 a_data: 'hfcd10bc0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h4 a_user: 'h1bd42 d_param: 'h0 d_source: 'h34 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2128.316325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 33472492060529100777109290409898221531430860921234148137526587839089522617135 217
UVM_ERROR @ 2582.510266 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@36869) { a_addr: 'h1051c a_data: 'hd60fd407 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h1ae5b d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2582.510266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 63915822666817669876842136877632236044427776152848654128072326341087552202978 224
UVM_ERROR @ 2139.563209 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31851) { a_addr: 'h10648 a_data: 'h3056013e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h1a29a d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2139.563209 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 54347453617524945943162016525329726281307036748164670862417497964934924777170 217
UVM_ERROR @ 2801.436776 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32871) { a_addr: 'h10440 a_data: 'h1eb43b17 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h1bd4b d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2801.436776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 87017238299471121573629041616211973052862530850867170789486271360242932193116 224
UVM_ERROR @ 2151.883255 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32435) { a_addr: 'h107c0 a_data: 'h5b751e07 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2b a_opcode: 'h4 a_user: 'h181ab d_param: 'h0 d_source: 'h2b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2151.883255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 100603844764400260605892355452975354823788083074180029375699813395118123234854 217
UVM_ERROR @ 2647.574096 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32049) { a_addr: 'h10554 a_data: 'hacc182f4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h4 a_user: 'h19279 d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2647.574096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 60340945134059062651628988448778124952165772312435499451837190156753022061108 224
UVM_ERROR @ 2133.806197 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32199) { a_addr: 'h106c4 a_data: 'h71f017f3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h18a38 d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2133.806197 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 15441929705270611865381539623011664991126795263837077043104732116832986342297 217
UVM_ERROR @ 2270.805298 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32495) { a_addr: 'h1056c a_data: 'hb437ce18 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h1baff d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2270.805298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 3689309921863995285361570873096717899270581405233937478176633019153671609331 224
UVM_ERROR @ 2163.295098 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@33877) { a_addr: 'h104a8 a_data: 'hc051026b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h1a93a d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2163.295098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 31738861267041631256056792772473692022124928144683751676559298361298221204888 217
UVM_ERROR @ 2260.527016 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32329) { a_addr: 'h107d4 a_data: 'h144843e8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h1a9c7 d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2260.527016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 25274671912014401663361234822625702459375079641003946847585508448623447063821 224
UVM_ERROR @ 2436.595675 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31723) { a_addr: 'h1062c a_data: 'h5d2e3b0e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1b a_opcode: 'h4 a_user: 'h19e0c d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2436.595675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 35046010436222581637665700008460431411913348784833763806843567359274773604978 217
UVM_ERROR @ 2396.613600 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@34779) { a_addr: 'h105d8 a_data: 'h300c5e05 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h1baf7 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2396.613600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 73014964063994888466273975155119188636819712835695989003031822717462671670981 217
UVM_ERROR @ 2070.617736 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32101) { a_addr: 'h10518 a_data: 'hadec3998 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h1a2b9 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2070.617736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 35779477923003264731112213485607258986414287092159671216221786965757057083823 224
UVM_ERROR @ 2178.883710 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31607) { a_addr: 'h10688 a_data: 'hc9f47524 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h35 a_opcode: 'h4 a_user: 'h1baff d_param: 'h0 d_source: 'h35 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2178.883710 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 8399387832397323168895246830507466585286404605066259886698431254358933847695 217
UVM_ERROR @ 2827.283716 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@33839) { a_addr: 'h10378 a_data: 'h5b56aefe a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h4 a_user: 'h18a91 d_param: 'h0 d_source: 'h2e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2827.283716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 7998185458348350918758158507686204513793997529437073687506720318972267589821 242
UVM_ERROR @ 5616.185310 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@211443) { a_addr: 'h106e8 a_data: 'h11cf1ffc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h15 a_opcode: 'h4 a_user: 'h18ace d_param: 'h0 d_source: 'h15 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 5616.185310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 55781026689712816730312590694754723783098789733931898438685811741109005993905 217
UVM_ERROR @ 2353.186700 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31937) { a_addr: 'h105f0 a_data: 'hd56de1b7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h1b6be d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2353.186700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 46767373819931729705630843705866706373773822078623555675956558643337135360348 224
UVM_ERROR @ 2419.095070 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31683) { a_addr: 'h10600 a_data: 'h46529c2a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h19ed6 d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2419.095070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 43884576935335356089288239412503455109847114497188842952426985998820733851939 217
UVM_ERROR @ 2436.333278 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32569) { a_addr: 'h10628 a_data: 'h4b95d369 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h192fd d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2436.333278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 28226037768621629667193835942950284926605400368850030685669957794928643188890 217
UVM_ERROR @ 2531.673120 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@39113) { a_addr: 'h10720 a_data: 'h869cc8aa a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h20 a_opcode: 'h4 a_user: 'h18164 d_param: 'h0 d_source: 'h20 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2531.673120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 32039218255055089401012885621008596093938823892737627461338570865070833827360 224
UVM_ERROR @ 2793.196389 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32049) { a_addr: 'h107e4 a_data: 'hce767f89 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h195fa d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2793.196389 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 81491891135729990695528369384847534094270978098413169138518467428392420227385 217
UVM_ERROR @ 2453.652486 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32247) { a_addr: 'h10358 a_data: 'h17313c55 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h19244 d_param: 'h0 d_source: 'h21 d_data: 'h7b302573 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd1f a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2453.652486 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 110210342550156212042733876786042312180686164914229709181546798384487390013089 217
UVM_ERROR @ 2624.359320 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@34429) { a_addr: 'h107d0 a_data: 'h7c583d7c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h19 a_opcode: 'h4 a_user: 'h1a51f d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2624.359320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 66389585543839537141321211422161109989417619140762465614326980082769348263362 217
UVM_ERROR @ 2113.922020 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32083) { a_addr: 'h105f0 a_data: 'h90fd82ca a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h1b69e d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2113.922020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 28064366935497444764549717849484029126875633779092420802682573517272865349176 217
UVM_ERROR @ 2154.677089 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@33127) { a_addr: 'h10530 a_data: 'hf1278ce4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h1aecc d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2154.677089 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 6047555756950462917976244152880186201456296656063164911387704102660527438435 217
UVM_ERROR @ 2431.270902 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32367) { a_addr: 'h1051c a_data: 'hf1b15186 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h1ae42 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2431.270902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 57634185408256332155402933503463923784443404686357554895085461525643618069542 217
UVM_ERROR @ 2265.017791 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@33717) { a_addr: 'h107d4 a_data: 'hc8bb36ce a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h1a9b1 d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2265.017791 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 64751148371342055473122443570690708809652272414241408638973315546480172446322 217
UVM_ERROR @ 2364.419505 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31979) { a_addr: 'h106ec a_data: 'h41ad6af6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h18603 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2364.419505 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 42516661413127964208207595531854406052093792032310654105755252295469364838367 217
UVM_ERROR @ 2103.277653 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@34735) { a_addr: 'h10794 a_data: 'hb51d7279 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h18175 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2103.277653 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 7643332429998667631659020952199404818428336137348748781317947312034780062716 217
UVM_ERROR @ 2155.675432 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@35131) { a_addr: 'h107a8 a_data: 'h4d9d17bf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h1a504 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2155.675432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 18427485156687228888620558483869350590767288574190345229771283546210442101626 217
UVM_ERROR @ 2246.158557 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@32539) { a_addr: 'h106fc a_data: 'h96da8914 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3b a_opcode: 'h4 a_user: 'h1a29f d_param: 'h0 d_source: 'h3b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2246.158557 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 107294193154308768009630258146738066952906248333509192199444056078297996352163 333
UVM_ERROR @ 4938.581027 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@131547) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 4938.581027 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 95609647560380826110997710616870818269043765278464797591810666974942153537585 333
UVM_ERROR @ 3872.330140 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@126563) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 3872.330140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 103746002462092127630855552341994559046873856332701540397289008362310044143886 333
UVM_ERROR @ 4997.652520 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@109907) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 4997.652520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 45918289723220168269839310951434779887896994982744515772972718260803623261812 215
UVM_ERROR @ 2906.265845 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105f0 read out mismatch
UVM_INFO @ 2906.265845 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 58244343014188412398922661337883042633295697145566557252049854334280839160765 245
UVM_ERROR @ 6427.571479 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10524 read out mismatch
UVM_INFO @ 6427.571479 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 49622732606963407467300677733223079124533530608372834738064883944904985039367 322
UVM_ERROR @ 3756.345966 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
chip_sw_spi_device_pass_through_collision 88703011498941372866600735380399972325114779049523968114136007262844073876074 322
UVM_ERROR @ 3433.706787 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 29648209209893655571011083122729830107285289157180041132945930769332054795207 309
UVM_ERROR @ 3065.611050 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 3065.611050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_flash_ctrl_lc_rw_en 89322193533902445518776989069697506434823844190073613982106566713094943925134 309
UVM_ERROR @ 3006.819398 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 3006.819398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_flash_ctrl_lc_rw_en 76375110495431541156376602667842434236733679902303917804777679222976645339321 309
UVM_ERROR @ 3085.936790 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 3085.936790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 34215889557508686648827373521816967315990954695079539275614221213506353953549 342
UVM_ERROR @ 7654.465523 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7654.465523 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 80934098083985084698185985949499261435925002926497842497301270256629166612598 342
UVM_ERROR @ 7349.760868 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7349.760868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 13185803936919346338771185217247075707556425099325525070304198167277890034477 342
UVM_ERROR @ 7662.976326 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7662.976326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 94044137890206866139036482130631550686978983292849093299945771274403661443520 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3413.790226 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3413.790226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 20852336394880135578181092922601306544519896851003310450352896458516171605410 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3360.468960 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3360.468960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 110346062562355632093126224616236788893503435635557196970625562640109625744349 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2575.487016 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2575.487016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 79717547135146227964154579461084236670325040806915961018259878067443923744881 317
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3228.669024 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3228.669024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 56307246247644891252121169882719002267520190946615111053938745003912448170204 317
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2940.923804 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2940.923804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 17362742075005737478885937283755126371803386028417290106600609582050557498053 317
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2964.624410 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2964.624410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 6499252677776675462410599784076846809620402362633255198571677998840251476264 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 107913367367357757695530931787095564498692521943213991908767664471619002303161 369
UVM_ERROR @ 8680.994519 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 8680.994519 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 49546969870880192192072662923325224405415224346284928368081640384352597965241 369
UVM_ERROR @ 11869.765896 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 11869.765896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 75685117997434750488302298856548081070225534563367512232831229293265745952081 341
UVM_ERROR @ 7615.538124 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 7615.538124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 11270236612491568307238098304134533603574695016152332014573130010754947055720 369
UVM_ERROR @ 8959.024936 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 8959.024936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 44689198325556124913734050730738978870351135381116636597011020142263080306763 369
UVM_ERROR @ 8564.554533 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 8564.554533 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 2681840976479074161607395420087219838687617651251687876630672332722265133396 341
UVM_ERROR @ 6134.079744 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 6134.079744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 14152217709813031579695161281019746879092071095077641625825401442542932804255 369
UVM_ERROR @ 10848.221448 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 10848.221448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 48163038695092630126987781930413717528448818033281039418379777334066648714772 369
UVM_ERROR @ 8967.812806 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 8967.812806 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 5267226273538447874002062939946027430273861916160345317990809632543591244029 341
UVM_ERROR @ 7113.188582 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 7113.188582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 47732322021829786778484552921513751534693370001004868529844830681475521918363 344
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 13036.952000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13036.952000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 24331098492463845709461057304219834242210936642963343402184038180538841129785 314
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6135.420000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6135.420000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 4867392590073253423412530687510439939246754904329703926355398333239079054883 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6918.876000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6918.876000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 109407184408781631745614765312533125115912041308989957251878994176146916115944 316
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 5963.597000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5963.597000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 8703190532010612426742303524430887161317743677471169992290537029626247397234 344
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 12284.791000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 12284.791000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 73563949279399322104003598101556028575149463346096912474766050264356935646987 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7665.710000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7665.710000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 75334680133093969313282527970873215746760831974294378311287013279155318700746 367
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 14299.062500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 14299.062500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 21701488492477616826289171983212401892131971411138223108021201655658299981427 319
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 8734.274000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8734.274000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 101529521190918984853014326231123081949377465943174624408670747665777199241586 327
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 9768.516000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9768.516000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_rv_timer_systick_test 28106601916330604724518845542527542346591537652231191361566048533172258796149 None
Job timed out after 120 minutes
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 82222553012518796335915082830899956438565365557525136058297682252629730326332 None
Job timed out after 60 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 58624419057903577454578723602470846135700446623218467999367182740271645092985 None
Job timed out after 240 minutes
chip_sw_rv_timer_systick_test 2541203236813661574445081704185087949045818887808719512580056685719844136649 None
Job timed out after 120 minutes
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 63505516038570888129423574892240913624363725076472665277261412076441696033731 None
Job timed out after 60 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 22051569559140469207983963221693421315299298763787983983903585943038556645434 None
Job timed out after 240 minutes
chip_sw_rv_timer_systick_test 67200397268533298861515231682400234452701067031511578510177692412675993494791 None
Job timed out after 120 minutes
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 30016553045536350572906796381663886582005281831921998833353931921115283169515 None
Job timed out after 60 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 86533614346539399832631860977237790909536329967679722979977682888884258192689 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:502)] CHECK-fail: Expect alert *!
chip_sw_alert_test 80464805813037743185499115367332525511499105990250018218199629147713547300599 307
UVM_ERROR @ 3332.614215 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:502)] CHECK-fail: Expect alert 49!
UVM_INFO @ 3332.614215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 75775605060712388078306303108756568520492367955099838305386513109690525073601 308
UVM_ERROR @ 3280.165800 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3280.165800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108403751074201021216360847447167202562780526250663840308609683246752441085206 308
UVM_ERROR @ 2978.733858 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2978.733858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 61655250063078286246982999838492590583643504839391616411900372411793532139961 308
UVM_ERROR @ 2696.702471 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2696.702471 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 99581774666063483288577963485386224175947392834539997270919332115271567333378 308
UVM_ERROR @ 2827.053556 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2827.053556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33400443904324811054462939106766285155669809655155455545546161775608210994555 308
UVM_ERROR @ 2418.629303 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2418.629303 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48439272529797435200127464904382203429763428660255154448281409691783258357176 308
UVM_ERROR @ 2541.263368 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2541.263368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16199194773963123112091804565188508067296380147885813270590152151118068904445 308
UVM_ERROR @ 2652.938196 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2652.938196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 99067135247722777976976923323471684279855492851884118878729423477728474461162 308
UVM_ERROR @ 3116.559053 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3116.559053 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62814505198592078578985132739487216679597825597618008330115130200506353667769 308
UVM_ERROR @ 3304.986175 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3304.986175 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102049560722609028583156826079393023337095102541361674933829718711418544852978 308
UVM_ERROR @ 3490.091660 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3490.091660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 53026200239830867567643863272984862529358112046617129748534493209862653829591 308
UVM_ERROR @ 3496.225448 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3496.225448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40428824390661745473905284223705780957635851951831231270857834480105307689845 308
UVM_ERROR @ 3056.447300 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3056.447300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 32445378918537485955680394969938310766574969625639148137089281022128558722515 308
UVM_ERROR @ 3319.947476 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3319.947476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 73237683477904107513289131292464757485599618070841981240202804503073421626804 308
UVM_ERROR @ 3002.670147 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3002.670147 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109285406704561566050773591535987101405766532022959221731300372140543871976958 308
UVM_ERROR @ 2944.718444 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2944.718444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88918571888165614570129530789820998984588152260612212594262870304717681177439 308
UVM_ERROR @ 2632.524480 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2632.524480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79519325775505431428187954568904561494792847224434282276884648850024995773693 308
UVM_ERROR @ 2512.917490 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2512.917490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62718625428188243689757246476400741400599190911842519598935727723629435776986 308
UVM_ERROR @ 2980.734830 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2980.734830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 103132441602776179138159041824042572049897912215971102996125106782106099947289 308
UVM_ERROR @ 2814.072572 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2814.072572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 95179710620315213846459092904471206307504370469631249453641757126684243078242 308
UVM_ERROR @ 2528.651230 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2528.651230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 398512013247716165173037967708936870717448641015798213112739655578208782749 308
UVM_ERROR @ 3337.198352 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3337.198352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 41329784639188859461160669984574149410803852519102909321720810891751490588148 308
UVM_ERROR @ 3220.668324 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3220.668324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88386960444960933280727746786829514830932569363931129403475774074450492012873 308
UVM_ERROR @ 3557.275600 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3557.275600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106404015720278850886838678391860924030719811394921032137005773513100213522495 308
UVM_ERROR @ 2904.539430 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2904.539430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 907110501278691546773092677184974460859099435100506818000780307331402857796 308
UVM_ERROR @ 2291.781116 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2291.781116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 21972369730554006020612471496590515534524063596001105220911580235504592407959 308
UVM_ERROR @ 2340.463704 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2340.463704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 9911723333845316646478173339964793619184190668542340427179678306827392542798 308
UVM_ERROR @ 3537.081350 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3537.081350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46669592048465371760434780297275433466206956187363573586625793848342013203253 308
UVM_ERROR @ 2927.029976 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2927.029976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106311640899056698254469461764471323755695418626599849261643846827216073476012 308
UVM_ERROR @ 3262.665569 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3262.665569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 66813683675148221227131514297995720707935417983898939875067575632002952532184 308
UVM_ERROR @ 3484.857142 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3484.857142 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77704122362378302065301259055678618934788987476628051180829767028643650660959 308
UVM_ERROR @ 3656.350240 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3656.350240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101021485828006146098896738998877679193285895686097728580346297890943152839812 308
UVM_ERROR @ 2865.802434 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2865.802434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16251671562705707038294664052280414421598719887145742059363341973260386083533 308
UVM_ERROR @ 2299.654416 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2299.654416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 58665630373941210087772365608266199357991900093078685418279793289757976759787 308
UVM_ERROR @ 3044.446388 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3044.446388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 99008703096840888724361349057188142836772019575204025642144540664705690414444 308
UVM_ERROR @ 2609.091260 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2609.091260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 18475145661102524271784523624784354332976862633024984619708359236954153341484 308
UVM_ERROR @ 2944.907732 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2944.907732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14119924503126758729089044442146857134155328835217510939053979211058307761114 308
UVM_ERROR @ 2789.840952 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2789.840952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 57400350699163985210587011324235720298175817109250562169998148765145299205197 308
UVM_ERROR @ 3139.038040 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3139.038040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78046481738688877411065588728487200971473098275339771043550425715683409989883 308
UVM_ERROR @ 2684.045114 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2684.045114 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 18122918117630656545507283441161318744181107223563674139861005081283634124157 308
UVM_ERROR @ 2869.055415 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2869.055415 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55734850317398039034026754477262529677991033408728060421083557544967523675597 308
UVM_ERROR @ 3262.223980 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3262.223980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101458322863087414295077595465227567537367629226930860575640418469081180437162 308
UVM_ERROR @ 2653.236615 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2653.236615 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35837798709680661420216987221362842824172646282768236977062441344212348737560 308
UVM_ERROR @ 2485.202870 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2485.202870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59539346781806025025194387320171338445265569604045556870768582380553892929547 308
UVM_ERROR @ 2542.271116 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2542.271116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89073794119834470996845007484115984847209475753299346941724497055017166274462 308
UVM_ERROR @ 2516.944230 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2516.944230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 104914079321869577082989600844577754786702708961085172654954242592465822355042 308
UVM_ERROR @ 2692.827590 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2692.827590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 15777446268419842538200978227203664910025304151873108325783460688181363154679 308
UVM_ERROR @ 3249.925560 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3249.925560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 38432900868290950889792779265058816227933533182588469294635495449670000960410 308
UVM_ERROR @ 3265.323900 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3265.323900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45890725380844754775113965685573685241733501244928233353510528533233165953220 308
UVM_ERROR @ 3147.417880 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3147.417880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 61697766531374189193875696578469802613754065276470008793447946065895174502229 308
UVM_ERROR @ 3448.606416 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3448.606416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 1126688814219901181757198771453631734136201069880485689239602656910126694844 308
UVM_ERROR @ 2811.581404 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2811.581404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 43722527646992331891057657338474597574724501026891459496400698248153777640671 308
UVM_ERROR @ 2992.478810 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2992.478810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 15647576580239919682379225799931909710070027168834218478731307514916531798108 308
UVM_ERROR @ 3126.517788 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3126.517788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70082182256793925429648742813872274853575070932602242160345841116904642132266 308
UVM_ERROR @ 2207.911710 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2207.911710 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14628318832763222369839126246495016940493674377694580363279777952922836791510 308
UVM_ERROR @ 3172.384374 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3172.384374 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45722034299250755420097032892040842955363695439166695690309034327876031190748 308
UVM_ERROR @ 2663.440488 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2663.440488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 103139717043555549619795690393017748361201510407679310341088973648968388686262 308
UVM_ERROR @ 2848.742540 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2848.742540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 53558197817945998624308341515433722835193846228099170417388844510100484870671 308
UVM_ERROR @ 3407.592820 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3407.592820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84756049332318824126990569850988198673777753161615156907030531855226324629770 308
UVM_ERROR @ 3111.211326 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3111.211326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 21493612188576731921504874518408847042611913732591270824891565436978844139474 308
UVM_ERROR @ 2571.674896 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2571.674896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 95986242685232128934285558895101610989956693855452321431245030120706972234849 308
UVM_ERROR @ 2802.120400 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2802.120400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106358539204305160869888454455737549512391138274541342143184864104974214721378 308
UVM_ERROR @ 2927.422680 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2927.422680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34189942358109617810248558251776379819356823157639759998400002164167287167997 308
UVM_ERROR @ 3311.648264 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3311.648264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 4300447676319271484534195994611916903216995977756369332677080394989452164423 308
UVM_ERROR @ 2905.972998 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2905.972998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 9685432020276100899571404635364152557428392786393972360170258165015132552981 308
UVM_ERROR @ 2603.810474 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2603.810474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40912401924254791942687155055256190569576197282919917646616589623164882396342 308
UVM_ERROR @ 2279.926585 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2279.926585 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88786147911485244285589894417883961069342457955294982808707807899283603825364 308
UVM_ERROR @ 3061.004302 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3061.004302 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 38232830408077786467043576535192309972246532673383561015469893338889325640284 308
UVM_ERROR @ 3103.158562 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3103.158562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 52854722776484734808355997890423701738664537136583871125133816528702737427700 308
UVM_ERROR @ 2984.364965 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2984.364965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 8939428250026314340427414003273466118147178797541186974516823237377510931053 308
UVM_ERROR @ 2702.286520 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2702.286520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89323725680479788964598375767650473596691808145540802488388059079724552066583 308
UVM_ERROR @ 2904.200880 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2904.200880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68278442489040646240192231865998434625856047945455316691251708840505694033795 308
UVM_ERROR @ 3044.219442 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3044.219442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39633605189308296202114968471254485434916840952113633083145000757719128964305 308
UVM_ERROR @ 3037.515816 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3037.515816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 63563475390865016421332885352215204428792484167119124765476167124652928886106 308
UVM_ERROR @ 2894.981558 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2894.981558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93888104488686587440231548826812269081565137264486268144478658881903702913263 308
UVM_ERROR @ 2828.426152 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2828.426152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40984533823377350943551107080412395557275495522256879718309071211791602101589 308
UVM_ERROR @ 3147.051960 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3147.051960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 37826634252877545161229564697380695651548645638111006657573233281053939760560 308
UVM_ERROR @ 2663.568030 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2663.568030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 1336890981796822885409373846249875800341788774007002495819668016243827524979 308
UVM_ERROR @ 2856.418556 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2856.418556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 21133890147560329017675319313963162152688692413695053413263690371569370766072 308
UVM_ERROR @ 2988.996984 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2988.996984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 90105840479471272263062428593529456937092863873753620904754961905972550657836 308
UVM_ERROR @ 3368.286616 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3368.286616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16647420939422245729932236727994029396057264036384515964547472552443603874491 308
UVM_ERROR @ 3566.451068 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3566.451068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46786917804016300135920299290219695063507625327601003737266927877276258178671 308
UVM_ERROR @ 3726.531200 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3726.531200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 103013052237455187576914353214115687112825675460216106707304029193334692275836 308
UVM_ERROR @ 3410.695552 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3410.695552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39650091063775449277997274672433180471145005785699106935449267205761386745696 308
UVM_ERROR @ 3244.356408 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3244.356408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 65157228244244006335749889454695825038998228125389912816392247925722240091283 308
UVM_ERROR @ 3611.158496 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3611.158496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 80361950420825199117365432593054601074072694888862187110275101604270736748433 308
UVM_ERROR @ 3242.234627 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3242.234627 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 5520292678375523370827662700040797580205579508793206936028306062590204441783 308
UVM_ERROR @ 3372.869006 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3372.869006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 91085124861997847631702854817641428584719268252262670046572203641227826884296 308
UVM_ERROR @ 3570.349893 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3570.349893 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34172108638312103094159455704125985286173222000349250369299684052323983062826 308
UVM_ERROR @ 2492.014768 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2492.014768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 115028603238755698595506427581475156808578132844287892340922531301318148979358 308
UVM_ERROR @ 2885.141740 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2885.141740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 21798242143907863661450829244051468915894918681486360834003337662310466285547 343
UVM_ERROR @ 3415.366972 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3415.366972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 41899860666395270973392010779750967443513453807896689173188680749318411107769 343
UVM_ERROR @ 3045.169599 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3045.169599 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 54117154343271403751837843985374673521498746583049644135157628245479573572847 343
UVM_ERROR @ 3998.976266 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3998.976266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 8956472058274730072164612677223618366128873115280318869329876061262406328312 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 55326016469781746692088209900213347806143128241106415394259114819840968776791 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 94932842444291492647009445132207684742923790856711650637705532874490535313931 None
---- STDERR ----
Another command (pid=1578114) is running. Waiting for it to complete on the server (server_pid=2727368)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 21959625560718119192978247756623881961050773433865760547631951680413672188956 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 7897257965785334413782804167840316273625762564972117045485711962826134170024 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 88614721731923444931554170307318433973271989669324277754398527303811185796273 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 39366626197861389006968955384284543699639969920182879171964477396696298555330 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 13801299956418581992097053570070195852043959870826055637136110795545534602812 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 8664823488762037848788617692412982717935311603029313954455786921445825823606 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 13463841636584203114679673115932967664967194247708984495885552098246049843273 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 22346793227001189556630745272995449323458048418389340954373696046505308070616 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 5907444375586629240151567439554686627491494689876251284274946663965952410297 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 51235496711165450589461349532655017295856355652153686146288970263308925480670 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 68423732768645081014495518115998446560671429288109293127184778993059433776183 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 31072823906419190005975893694894443471571139438347866340991000069449818382788 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 38402286030937260162272321014012941559617178383335710054286360947992116641346 331
UVM_FATAL @ 1951.538000 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 1951.538000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_core_ibex_lockstep_glitch 36056803954556713474520463897071657936562191565896566429420777570528010466344 327
UVM_FATAL @ 2635.538738 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2635.538738 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 5984700231154175482843360542309089869925162914842998681286781458373793749775 314
UVM_ERROR @ 4080.927000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 4080.927000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 112351677901041871516970702100443470232131973595546928718944391887753089838618 312
UVM_ERROR @ 3105.915500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3105.915500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 15323928069753308811537285310468840733410702775550449359866782284406057876648 312
UVM_ERROR @ 2790.867500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 2790.867500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 35522650757468483805628344186408365699472179420593264394211863205572626361849 318
UVM_ERROR @ 3008.996000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3008.996000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 107288738747536561467031901177233978129067933505837797437554011637388152005075 318
UVM_ERROR @ 3520.404000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3520.404000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 104548786627280424919868567334243085056946644438390237978728264156008080404630 318
UVM_ERROR @ 3280.355000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3280.355000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 80208644355925920387398625488755429885425159169400994586408211929935593245175 327
UVM_ERROR @ 15035.125533 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 15035.125533 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 48172037074913837865927335787810039129150296979362535713093950758805363509767 327
UVM_ERROR @ 15440.880331 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 15440.880331 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 62799569465479909166475390351749499021464269523940308588851270544120168661927 327
UVM_ERROR @ 10397.836480 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 10397.836480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 49933960924025144695435596254941374213152098549949063339481859707888202114546 350
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 22721633684109767731697343580010641227522672087535612551228267474545090291223 350
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 71785664631320603141615574697089708955951036293475607147135373285257889540298 349
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 12301887973670798104219370990847900462894273015424758098762859344410455101076 351
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 99243036040079165593436411420848582161383890177807572312790326417373976748639 349
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 70901184821365144786561594496307804651342746955655368719798319527824336707849 347
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 79754789139123838930802654659197586019423135250175846720742253773161788635043 347
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 67780378422395615961845648506396292751746073669901611818355429813847547602879 347
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 81868234737020948815100692295892582752194381707032109553145969679196792002964 348
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 89657795152403564102157531969331788180632360284761093415236971032019559212484 347
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 54901869199476656769197958489884954132933969723849765366642684148624751895381 359
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 61391924527006423094153677034320900142095770822879716574396398567056431581979 359
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 104529614070423960504333509320478603012611005750644344354760745894094754347215 360
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 101935118691444785329234599040781706022979634517188337299990969519223966093177 325
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 26712676555838080573975194699631850543064051602214802745760560064174961756796 323
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 63828310992183067847979781396071505677355016125793064494475441633116931541730 324
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 100238079871944204338151574935152516689381287815738500451340562906384104192442 357
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 40039831093982658949752375700506970175388930631934523491939852048378159042374 324
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 76652533008214638967061903796702053745335305047513188463439986858587923271970 358
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 105662680548201561593677430173231798431936934001901538539779359246531922642965 324
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 79031035497720720074222223721325247054473778409293888335920028996411507078024 323
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 5179743173419247126680370983996053097586517447702742057832811486699289560878 323
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17891126194615844028231850777131335717186329262542928955867521591521563971800 324
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 72960488635189884894040431926688724647866105574287410310833208077585430227780 323
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 58682013105775390287360340812007622198985401641325890286983027956110264673570 323
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
rom_raw_unlock 20731943925645029602693913857989384593344437146253902314868084637262781666201 322
UVM_FATAL @ 15035.342942 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
UVM_INFO @ 15035.342942 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 11117210358690764176178241424557472947166371553801696309153858296606596679840 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 5091.701900 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5091.701900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 18063976195589012621773612154441370084084852485934298469450366074808778959429 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 4215.470264 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4215.470264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 45192023276634446035531027693495315544294319849974798590724809091117986305548 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 4665.759945 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4665.759945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 45654537293817938336273407263783456559323554704561002136883084334803641839666 320
UVM_ERROR @ 3355.894147 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3355.894147 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otbn_mem_scramble_test_sim_dv(sw/device/tests/otbn_mem_scramble_test.c:255)] CHECK-fail: Expecting at least * IMEM integrity errors, got *
chip_sw_otbn_mem_scramble 50634929080137136146923642943640455016462783472937531396544901801458308478954 310
UVM_ERROR @ 3938.060386 us: (sw_logger_if.sv:526) [otbn_mem_scramble_test_sim_dv(sw/device/tests/otbn_mem_scramble_test.c:255)] CHECK-fail: Expecting at least 48 IMEM integrity errors, got 47
UVM_INFO @ 3938.060386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!
chip_sw_alert_test 12763495282228600395062241423289131106376601954367679969284980935556538594260 307
UVM_ERROR @ 2711.640024 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert 51!
UVM_INFO @ 2711.640024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 108160285272529708885422832220930582975123840293168803033345916431916560935719 319
UVM_ERROR @ 17072.168523 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 17072.168523 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 22469809289484567329772705311763915618845287690763562815752427785805095932282 341
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 8400403248ps failed at 8400403248ps
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 8400486576ps failed at 8400486576ps
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert *!
chip_sw_alert_test 70575978236785995741944887760370639000726450394003939034239204617713213122918 307
UVM_ERROR @ 3192.881176 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert 56!
UVM_INFO @ 3192.881176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
chip_sw_all_escalation_resets 100870640440712941006426945177675578754364153603782794300329464563056655134241 316
UVM_ERROR @ 3184.567656 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 3184.567656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 48050024863223020005256191230489461445415082314628528559709305229382822268105 316
UVM_ERROR @ 3154.697298 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 3154.697298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 79169412322959660986023270329003540275142325840376806312291586974773863928902 316
UVM_ERROR @ 3256.955340 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 3256.955340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 28576442632545681888918893101951010647605148111163126115965158532576411156883 316
UVM_ERROR @ 3255.910920 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 3255.910920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 66587268555892804482447602761125811778077244336503094929301364731861410948852 316
UVM_ERROR @ 3598.642256 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 3598.642256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *
chip_sw_all_escalation_resets 49890630189727140952078603353674081850497540466843927676255766269120549875789 317
UVM_ERROR @ 3008.356420 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3008.356420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 45285702721936193478544171843728859294334463552243610102875536067417255535189 317
UVM_ERROR @ 3376.009794 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3376.009794 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 105071301957519766616328123794791245314113769228828854353965311624350133016429 317
UVM_ERROR @ 2934.380750 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2934.380750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 21207080644013127745757893519149733030219473318006861272969105334844555002565 317
UVM_ERROR @ 3241.359110 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3241.359110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 12185357736306749419141408820845544596707572656185494552501100915375002887685 317
UVM_ERROR @ 2985.556531 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2985.556531 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---