Simulation Results: csrng

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.46 %
  • code
  • 96.33 %
  • assert
  • 95.85 %
  • func
  • 91.21 %
  • block
  • 98.73 %
  • line
  • 99.64 %
  • branch
  • 96.80 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.69%
V2S
99.90%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 6.000s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 2.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 3.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 38.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 4.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 3.000s 0.000us 20 20 100.00
csrng_csr_aliasing 4.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
alerts 500 500 100.00
csrng_alert 42.000s 0.000us 500 500 100.00
err 500 500 100.00
csrng_err 4.000s 0.000us 500 500 100.00
cmds 50 50 100.00
csrng_cmds 258.000s 0.000us 50 50 100.00
life cycle 50 50 100.00
csrng_cmds 258.000s 0.000us 50 50 100.00
stress_all 45 50 90.00
csrng_stress_all 810.000s 0.000us 45 50 90.00
intr_test 50 50 100.00
csrng_intr_test 2.000s 0.000us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 4.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 15.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 15.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 2.000s 0.000us 5 5 100.00
csrng_csr_rw 3.000s 0.000us 20 20 100.00
csrng_csr_aliasing 4.000s 0.000us 5 5 100.00
csrng_same_csr_outstanding 4.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 2.000s 0.000us 5 5 100.00
csrng_csr_rw 3.000s 0.000us 20 20 100.00
csrng_csr_aliasing 4.000s 0.000us 5 5 100.00
csrng_same_csr_outstanding 4.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_tl_intg_err 13.000s 0.000us 20 20 100.00
csrng_sec_cm 4.000s 0.000us 5 5 100.00
sec_cm_config_regwen 70 70 100.00
csrng_csr_rw 3.000s 0.000us 20 20 100.00
csrng_regwen 3.000s 0.000us 50 50 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 42.000s 0.000us 500 500 100.00
sec_cm_intersig_mubi 45 50 90.00
csrng_stress_all 810.000s 0.000us 45 50 90.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 4.000s 0.000us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 4.000s 0.000us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 4.000s 0.000us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 4.000s 0.000us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 4.000s 0.000us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 42.000s 0.000us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
sec_cm_constants_lc_gated 45 50 90.00
csrng_stress_all 810.000s 0.000us 45 50 90.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 42.000s 0.000us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 13.000s 0.000us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 4.000s 0.000us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
csrng_sec_cm 4.000s 0.000us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 17.000s 0.000us 200 200 100.00
csrng_err 4.000s 0.000us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
csrng_stress_all_with_rand_reset 398.000s 0.000us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 76811689064473829460994982611403174930615457964916705198895344341751673179941 137
UVM_ERROR @ 753962534 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 753962534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 114929060031242804637854528898759824779221424982152349837373577835144137152200 142
UVM_ERROR @ 178049237 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 178049237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 55632830687941634171192470025182710858759257054308882446680862383501949057274 168
UVM_ERROR @ 1650727449 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 1650727449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 42311991036406436371083184011688785732246893578962215263668630556338979677692 139
UVM_ERROR @ 7307824788 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 7307824788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 14462203543436672045956249472963218128044039483889822542986018090110820671341 146
UVM_ERROR @ 8417301736 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 8417301736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---