Simulation Results: edn/edn1

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.10 %
  • code
  • 95.93 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.370s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.080s 0.000us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.100s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.610s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.770s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.100s 0.000us 20 20 100.00
edn_csr_aliasing 1.610s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 48.470s 0.000us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 48.470s 0.000us 300 300 100.00
genbits 300 300 100.00
edn_genbits 48.470s 0.000us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.610s 0.000us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.670s 0.000us 200 200 100.00
errs 100 100 100.00
edn_err 1.650s 0.000us 100 100 100.00
disable 100 100 100.00
edn_disable 1.250s 0.000us 50 50 100.00
edn_disable_auto_req_mode 1.620s 0.000us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 5.910s 0.000us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.120s 0.000us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 3.720s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.470s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.470s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.080s 0.000us 5 5 100.00
edn_csr_rw 1.100s 0.000us 20 20 100.00
edn_csr_aliasing 1.610s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.490s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.080s 0.000us 5 5 100.00
edn_csr_rw 1.100s 0.000us 20 20 100.00
edn_csr_aliasing 1.610s 0.000us 5 5 100.00
edn_same_csr_outstanding 1.490s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 2.810s 0.000us 20 20 100.00
edn_sec_cm 6.630s 0.000us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.330s 0.000us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.670s 0.000us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.630s 0.000us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.630s 0.000us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.630s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.630s 0.000us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.670s 0.000us 200 200 100.00
edn_sec_cm 6.630s 0.000us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.670s 0.000us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.810s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 49 50 98.00
edn_stress_all_with_rand_reset 96.470s 0.000us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1149) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
edn_stress_all_with_rand_reset 33212025347329343700272397874760611746277269328500027046129306567940415797576 136
UVM_ERROR @ 569303004 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 569303004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---