Simulation Results

Simulation Results: flash_ctrl

29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.98 %

code
95.82 %

assert
96.76 %

func
98.36 %

line
96.10 %

branch
97.42 %

cond
94.80 %

toggle
98.26 %

FSM
92.52 %

Validation stages

V1		100.00%
V2		98.86%
V2S		99.03%
V3		100.00%
unmapped		100.00%

145/145 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	122.690s	0.000us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	22.700s	0.000us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	34.410s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	17.330s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	49.300s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	50.300s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	16.200s	0.000us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	17.330s	0.000us	20	20	100.00
	flash_ctrl_csr_aliasing	50.300s	0.000us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	12.420s	0.000us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	13.610s	0.000us	5	5	100.00

1123/1136 passed

98.86 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	16.040s	0.000us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	54.180s	0.000us	5	5	100.00
rma_hw_if				42	43	97.67
	flash_ctrl_hw_rma	1817.570s	0.000us	2	3	66.67
	flash_ctrl_hw_rma_reset	1068.790s	0.000us	20	20	100.00
	flash_ctrl_lcmgr_intg	13.780s	0.000us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	2196.570s	0.000us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	310.460s	0.000us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	203.410s	0.000us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	2975.020s	0.000us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	85.360s	0.000us	5	5	100.00
rd_buff_eviction_w_ecc				95	100	95.00
	flash_ctrl_rw_evict	31.000s	0.000us	39	40	97.50
	flash_ctrl_rw_evict_all_en	31.150s	0.000us	36	40	90.00
	flash_ctrl_re_evict	33.450s	0.000us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	297.940s	0.000us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	297.940s	0.000us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	431.240s	0.000us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	29.870s	0.000us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	710.430s	0.000us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	678.030s	0.000us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	574.530s	0.000us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1353.580s	0.000us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	13.540s	0.000us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	162.580s	0.000us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	22.580s	0.000us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	16.590s	0.000us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	831.040s	0.000us	5	5	100.00
secret_partition				128	130	98.46
	flash_ctrl_hw_sec_otp	215.390s	0.000us	50	50	100.00
	flash_ctrl_otp_reset	117.530s	0.000us	78	80	97.50
isolation_partition				2	3	66.67
	flash_ctrl_hw_rma	1817.570s	0.000us	2	3	66.67
interrupts				99	100	99.00
	flash_ctrl_intr_rd	224.460s	0.000us	39	40	97.50
	flash_ctrl_intr_wr	107.580s	0.000us	10	10	100.00
	flash_ctrl_intr_rd_slow_flash	392.930s	0.000us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	347.700s	0.000us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	75.980s	0.000us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	70.850s	0.000us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	18.580s	0.000us	5	5	100.00
	flash_ctrl_ro_derr	133.090s	0.000us	10	10	100.00
	flash_ctrl_rw_derr	194.440s	0.000us	10	10	100.00
	flash_ctrl_derr_detect	150.650s	0.000us	5	5	100.00
	flash_ctrl_integrity	533.320s	0.000us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	20.380s	0.000us	5	5	100.00
	flash_ctrl_ro_serr	122.040s	0.000us	10	10	100.00
	flash_ctrl_rw_serr	188.060s	0.000us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	78.620s	0.000us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	95.550s	0.000us	5	5	100.00
scramble				59	62	95.16
	flash_ctrl_wo	2648.680s	0.000us	19	20	95.00
	flash_ctrl_write_word_sweep	10.300s	0.000us	1	1	100.00
	flash_ctrl_read_word_sweep	8.780s	0.000us	1	1	100.00
	flash_ctrl_ro	118.240s	0.000us	20	20	100.00
	flash_ctrl_rw	473.870s	0.000us	18	20	90.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	37.850s	0.000us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	840.200s	0.000us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	159.110s	0.000us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	14.090s	0.000us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	13.430s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	20.600s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	20.600s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	34.410s	0.000us	5	5	100.00
	flash_ctrl_csr_rw	17.330s	0.000us	20	20	100.00
	flash_ctrl_csr_aliasing	50.300s	0.000us	5	5	100.00
	flash_ctrl_same_csr_outstanding	24.290s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	34.410s	0.000us	5	5	100.00
	flash_ctrl_csr_rw	17.330s	0.000us	20	20	100.00
	flash_ctrl_csr_aliasing	50.300s	0.000us	5	5	100.00
	flash_ctrl_same_csr_outstanding	24.290s	0.000us	20	20	100.00

V2S

815/823 passed

99.03 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.320s	0.000us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.320s	0.000us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.320s	0.000us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.320s	0.000us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	86.690s	0.000us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_tl_intg_err	549.690s	0.000us	20	20	100.00
	flash_ctrl_sec_cm	1981.170s	0.000us	5	5	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	549.690s	0.000us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	549.690s	0.000us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	31.820s	0.000us	3	3	100.00
	flash_ctrl_wr_intg	11.160s	0.000us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	122.690s	0.000us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				258	260	99.23
	flash_ctrl_otp_reset	117.530s	0.000us	78	80	97.50
	flash_ctrl_disable	22.580s	0.000us	50	50	100.00
	flash_ctrl_sec_info_access	86.360s	0.000us	50	50	100.00
	flash_ctrl_connect	16.590s	0.000us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	12.820s	0.000us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	17.330s	0.000us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.320s	0.000us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	17.330s	0.000us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.320s	0.000us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	17.330s	0.000us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.320s	0.000us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	22.580s	0.000us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	31.820s	0.000us	3	3	100.00
	flash_ctrl_access_after_disable	13.430s	0.000us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	19.830s	0.000us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	22.580s	0.000us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	29.870s	0.000us	10	10	100.00
sec_cm_mem_scramble				18	20	90.00
	flash_ctrl_rw	473.870s	0.000us	18	20	90.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	188.060s	0.000us	10	10	100.00
	flash_ctrl_rw_derr	194.440s	0.000us	10	10	100.00
	flash_ctrl_integrity	533.320s	0.000us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				2	3	66.67
	flash_ctrl_hw_rma	1817.570s	0.000us	2	3	66.67
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	1981.170s	0.000us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	1981.170s	0.000us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	1981.170s	0.000us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	1981.170s	0.000us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	22.270s	0.000us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				2	5	40.00
	flash_ctrl_phy_host_grant_err	12.570s	0.000us	2	5	40.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	13.110s	0.000us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	1981.170s	0.000us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	1981.170s	0.000us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	1981.170s	0.000us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	25.180s	0.000us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	671.130s	0.000us	3	3	100.00

Error Messages

	Test	seed	line	log context
Offending '$fell(src_ack_o)'
	flash_ctrl_hw_rma	93805461834684740971698628172385849503218052144692486284890455282867448236712	175	Offending '$fell(src_ack_o)' UVM_ERROR @ 88938366.7 ns: (prim_sync_reqack.sv:349) [ASSERT FAILED] SyncReqAckHoldReq UVM_INFO @ 88938366.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
	flash_ctrl_phy_host_grant_err	37543810897239237180116716423762226464200995039921957167480319384470230137941	125	Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' UVM_ERROR @ 5341.3 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 5341.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	85338875875239457469883078580009361351508497608876652993160318087071621070554	125	Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' UVM_ERROR @ 20361.1 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 20361.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	18750940883355639884407098773903986898471165385029939665365027789606986364231	125	Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' UVM_ERROR @ 27795.7 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 27795.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal_err triggered unexpectedly
	flash_ctrl_rw	67590326743376567458912831169678879807328709335353506982277305074465126323050	108	UVM_ERROR @ 151152.0 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly UVM_INFO @ 151152.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'dst_req_o'
	flash_ctrl_otp_reset	7846441337900214405977144924657930736347751766455529911158796597308585712274	218	Offending 'dst_req_o' UVM_ERROR @ 38846.5 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 38846.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_otp_reset	53947405089887470584843679183950472132865270316763529641675999672631812326448	152	Offending 'dst_req_o' UVM_ERROR @ 39498.8 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 39498.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:
	flash_ctrl_rw_evict_all_en	62238746217095687625653733637025190292990542794523361695751636849769433569255	108	UVM_ERROR @ 9604.5 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 9604.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	85286275196848477030135422800464092490311110095771145039105808598856090186494	108	UVM_ERROR @ 18698.5 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 18698.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	50888428464623185425032186331954524366745317419828556758272483766140669700920	108	UVM_ERROR @ 36755.4 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 36755.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	72580493556586897505146357854426260891865035259711556147796839884550863032186	108	UVM_ERROR @ 16112.9 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 16112.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	103934736588142109385007551851169500813756485063132873387851742507127266777186	108	UVM_ERROR @ 51732.4 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 51732.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue
	flash_ctrl_wo	11716875633427344672701531628024465348840887904246564898777499150698981800385	108	UVM_FATAL @ 200000000.0 ns: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000.0 ns hit, indicating a probable testbench issue UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	flash_ctrl_rw	40601553089092556330130202389630994768830084270709799685733704902982955925268	None	Job timed out after 60 minutes
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp f985_45831c82:ffffffff_45831c* mismatch!!
	flash_ctrl_intr_rd	27268404052476906732248470463460990631548090484698632232780241799148435140750	108	UVM_ERROR @ 979859.2 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 2: obs:exp 6043f985_45831c82:ffffffff_45831c82 mismatch!! UVM_INFO @ 979859.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---