Simulation Results: kmac/masked

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.88 %
  • code
  • 94.67 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 82.39 %
Validation stages
V1
99.29%
V2
99.76%
V2S
99.39%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
kmac_smoke 127.030s 0.000us 49 50 98.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.610s 0.000us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.550s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 21.520s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 8.160s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.880s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.550s 0.000us 20 20 100.00
kmac_csr_aliasing 8.160s 0.000us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.170s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.840s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3344.160s 0.000us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1385.690s 0.000us 50 50 100.00
test_vectors 39 40 97.50
kmac_test_vectors_sha3_224 2288.710s 0.000us 5 5 100.00
kmac_test_vectors_sha3_256 2368.420s 0.000us 5 5 100.00
kmac_test_vectors_sha3_384 1700.270s 0.000us 5 5 100.00
kmac_test_vectors_sha3_512 1008.270s 0.000us 5 5 100.00
kmac_test_vectors_shake_128 2337.210s 0.000us 5 5 100.00
kmac_test_vectors_shake_256 1905.900s 0.000us 5 5 100.00
kmac_test_vectors_kmac 3.850s 0.000us 4 5 80.00
kmac_test_vectors_kmac_xof 3.790s 0.000us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 510.120s 0.000us 50 50 100.00
app 50 50 100.00
kmac_app 385.100s 0.000us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 308.560s 0.000us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 432.010s 0.000us 50 50 100.00
error 50 50 100.00
kmac_error 536.340s 0.000us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 16.110s 0.000us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 8.880s 0.000us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 43.430s 0.000us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 29.730s 0.000us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 59.680s 0.000us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 31.620s 0.000us 50 50 100.00
stress_all 49 50 98.00
kmac_stress_all 2637.560s 0.000us 49 50 98.00
intr_test 50 50 100.00
kmac_intr_test 1.250s 0.000us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.250s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.470s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.470s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.610s 0.000us 5 5 100.00
kmac_csr_rw 1.550s 0.000us 20 20 100.00
kmac_csr_aliasing 8.160s 0.000us 5 5 100.00
kmac_same_csr_outstanding 3.120s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.610s 0.000us 5 5 100.00
kmac_csr_rw 1.550s 0.000us 20 20 100.00
kmac_csr_aliasing 8.160s 0.000us 5 5 100.00
kmac_same_csr_outstanding 3.120s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.740s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.740s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.740s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.740s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.740s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 5.670s 0.000us 20 20 100.00
kmac_sec_cm 92.260s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.670s 0.000us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 31.620s 0.000us 50 50 100.00
sec_cm_sw_key_key_masking 49 50 98.00
kmac_smoke 127.030s 0.000us 49 50 98.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 510.120s 0.000us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.740s 0.000us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 92.260s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 92.260s 0.000us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 92.260s 0.000us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 49 50 98.00
kmac_smoke 127.030s 0.000us 49 50 98.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 31.620s 0.000us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 92.260s 0.000us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 379.360s 0.000us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 49 50 98.00
kmac_smoke 127.030s 0.000us 49 50 98.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 293.300s 0.000us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_test_vectors_kmac 111442380253316365593882152242668816017921052110541258996948112347530484722219 78
UVM_ERROR @ 95376726 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 95376726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_smoke 28604383027291153445738824994999251560697683226541520170669937385120793264994 77
UVM_ERROR @ 195860212 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 195860212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 43241692845563535988252226128177164645111782991072645078762669557389896541032 199
UVM_ERROR @ 57377474273 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 57377474273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 18965584349240140605027113950761048845610463641684203274874422782857967868102 451
UVM_ERROR @ 3282166492 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3282166492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---