| V1 |
|
95.04% |
| V2 |
|
91.01% |
| V2S |
|
94.50% |
| V3 |
|
0.99% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| otp_ctrl_wake_up | 1.640s | 0.000us | 1 | 1 | 100.00 | |
| smoke | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 17.040s | 0.000us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 3.670s | 0.000us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| otp_ctrl_csr_rw | 2.510s | 0.000us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_bit_bash | 9.740s | 0.000us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_aliasing | 4.980s | 0.000us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 13 | 20 | 65.00 | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 4.150s | 0.000us | 13 | 20 | 65.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| otp_ctrl_csr_rw | 2.510s | 0.000us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 4.980s | 0.000us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| otp_ctrl_mem_walk | 2.080s | 0.000us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| otp_ctrl_mem_partial_access | 2.090s | 0.000us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dai_access_partition_walk | 1 | 1 | 100.00 | |||
| otp_ctrl_partition_walk | 18.570s | 0.000us | 1 | 1 | 100.00 | |
| init_fail | 286 | 300 | 95.33 | |||
| otp_ctrl_init_fail | 7.640s | 0.000us | 286 | 300 | 95.33 | |
| partition_check | 22 | 60 | 36.67 | |||
| otp_ctrl_background_chks | 48.050s | 0.000us | 6 | 10 | 60.00 | |
| otp_ctrl_check_fail | 22.660s | 0.000us | 16 | 50 | 32.00 | |
| regwen_during_otp_init | 50 | 50 | 100.00 | |||
| otp_ctrl_regwen | 9.950s | 0.000us | 50 | 50 | 100.00 | |
| partition_lock | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 42.250s | 0.000us | 50 | 50 | 100.00 | |
| interface_key_check | 50 | 50 | 100.00 | |||
| otp_ctrl_parallel_key_req | 67.390s | 0.000us | 50 | 50 | 100.00 | |
| lc_interactions | 250 | 250 | 100.00 | |||
| otp_ctrl_parallel_lc_req | 23.540s | 0.000us | 50 | 50 | 100.00 | |
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| otp_dai_errors | 48 | 50 | 96.00 | |||
| otp_ctrl_dai_errs | 82.260s | 0.000us | 48 | 50 | 96.00 | |
| otp_macro_errors | 14 | 50 | 28.00 | |||
| otp_ctrl_macro_errs | 47.570s | 0.000us | 14 | 50 | 28.00 | |
| test_access | 50 | 50 | 100.00 | |||
| otp_ctrl_test_access | 221.950s | 0.000us | 50 | 50 | 100.00 | |
| stress_all | 32 | 50 | 64.00 | |||
| otp_ctrl_stress_all | 470.720s | 0.000us | 32 | 50 | 64.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| otp_ctrl_intr_test | 2.500s | 0.000us | 50 | 50 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| otp_ctrl_alert_test | 10.870s | 0.000us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_errors | 9.760s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_errors | 9.760s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 3.670s | 0.000us | 5 | 5 | 100.00 | |
| otp_ctrl_csr_rw | 2.510s | 0.000us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 4.980s | 0.000us | 5 | 5 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 5.400s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 3.670s | 0.000us | 5 | 5 | 100.00 | |
| otp_ctrl_csr_rw | 2.510s | 0.000us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 4.980s | 0.000us | 5 | 5 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 5.400s | 0.000us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| tl_intg_err | 23 | 25 | 92.00 | |||
| otp_ctrl_tl_intg_err | 23.600s | 0.000us | 20 | 20 | 100.00 | |
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| prim_count_check | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| prim_fsm_check | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_intg_err | 23.600s | 0.000us | 20 | 20 | 100.00 | |
| sec_cm_secret_mem_scramble | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 17.040s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_digest | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 17.040s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_dai_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_kdi_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_lci_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_part_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_scrmbl_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_timer_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_dai_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_kdi_seed_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_kdi_entropy_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_lci_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_part_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_scrmbl_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_timer_integ_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_timer_cnsty_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_timer_lfsr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_dai_fsm_local_esc | 203 | 205 | 99.02 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_lci_fsm_local_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_kdi_fsm_local_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_part_fsm_local_esc | 214 | 250 | 85.60 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_macro_errs | 47.570s | 0.000us | 14 | 50 | 28.00 | |
| sec_cm_scrmbl_fsm_local_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_timer_fsm_local_esc | 203 | 205 | 99.02 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_dai_fsm_global_esc | 203 | 205 | 99.02 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_lci_fsm_global_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_kdi_fsm_global_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_part_fsm_global_esc | 214 | 250 | 85.60 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_macro_errs | 47.570s | 0.000us | 14 | 50 | 28.00 | |
| sec_cm_scrmbl_fsm_global_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_timer_fsm_global_esc | 203 | 205 | 99.02 | |||
| otp_ctrl_parallel_lc_esc | 33.490s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_part_data_reg_integrity | 286 | 300 | 95.33 | |||
| otp_ctrl_init_fail | 7.640s | 0.000us | 286 | 300 | 95.33 | |
| sec_cm_part_data_reg_bkgn_chk | 16 | 50 | 32.00 | |||
| otp_ctrl_check_fail | 22.660s | 0.000us | 16 | 50 | 32.00 | |
| sec_cm_part_mem_regren | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 42.250s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_sw_unreadable | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 42.250s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_sw_unwritable | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 42.250s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_lc_part_mem_sw_noaccess | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 42.250s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_access_ctrl_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 42.250s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 17.040s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 42.250s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_test_bus_lc_gated | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 17.040s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_test_tl_lc_gate_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 310.490s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_direct_access_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_regwen | 9.950s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_check_trigger_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 17.040s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_check_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 17.040s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_macro_mem_integrity | 14 | 50 | 28.00 | |||
| otp_ctrl_macro_errs | 47.570s | 0.000us | 14 | 50 | 28.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| otp_ctrl_low_freq_read | 1 | 1 | 100.00 | |||
| otp_ctrl_low_freq_read | 9.460s | 0.000us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 100 | 0.00 | |||
| otp_ctrl_stress_all_with_rand_reset | 32.120s | 0.000us | 0 | 100 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | ||||
| otp_ctrl_csr_mem_rw_with_rand_reset | 69328974887339780893613664916526538999949964849376905965325144091967342711268 | 92 |
UVM_ERROR @ 105588938 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 105588938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 1101441951859536050765696078766401774064056588367676247619979055309042604724 | 98 |
UVM_ERROR @ 250271784 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 250271784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 40890306802895672469253683323017668864336874184515304891028228522408858110856 | 92 |
UVM_ERROR @ 27103967 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27103967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 38518120685420380654090213304048886694761772457265419134171846295221970950661 | 92 |
UVM_ERROR @ 34743848 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 34743848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 1849255498017354744269141673059189686662443834264359489964968927992737523741 | 92 |
UVM_ERROR @ 65512754 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 65512754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 66152602438130582851669549743379081386157375695252985976266731977252006017171 | 107 |
UVM_ERROR @ 61147591 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 61147591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 92454018904540432458666678258976991242361897305306769289639865823932481143683 | 218 |
UVM_ERROR @ 72070188 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 72070188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 41540750717047719074167930364454703509839962403835376196677213513663121560471 | 121 |
UVM_ERROR @ 111358943 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 111358943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 40115931885631754298634407858831808226422776566379933020787269461527741681322 | 101 |
UVM_ERROR @ 108958528 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 108958528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 105736656450935455938773548489515197819106104924361402252990492968998235854372 | 92 |
UVM_ERROR @ 72791307 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 72791307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 78225992898733057386194840032246819925068890643995462777898691289013593176714 | 103 |
UVM_ERROR @ 28771667 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28771667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 79614944649698251981716301935358388442673776696062758814895539921360849243446 | 1368 |
UVM_ERROR @ 197735648 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 197735648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 71829509758026271961824760076933456840950574877295121507809191292312120979574 | 92 |
UVM_ERROR @ 62419025 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 62419025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 58169219995336516141076430526440140079186063901773436592338518264056586661388 | 93 |
UVM_ERROR @ 104443883 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 104443883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 4697401400619819557243794062129425779862778088626856019387982880877408566763 | 97 |
UVM_ERROR @ 28572184 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28572184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 62905620705987861160232306005626516756181980106864002991827340722333138248081 | 93 |
UVM_ERROR @ 52025817 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 52025817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 83319558280452699945012597107567919658762406652188893364119062365899996032756 | 95 |
UVM_ERROR @ 102583539 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 102583539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 91280866538162795649606993750633391899517851712635987756004198801046616234680 | 97 |
UVM_ERROR @ 26434570 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26434570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 22100161638314170716782266528530498168867569637737764889421036687029547040992 | 92 |
UVM_ERROR @ 121924869 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 121924869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 37292525114914860144100132377225375568638334090348013124273767211818220841062 | 95 |
UVM_ERROR @ 28322347 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28322347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 40918250383794456466274575708713686484234027889084773880406942910213568227688 | 93 |
UVM_ERROR @ 110934049 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 110934049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 81356501316661866319296671480244254600479934575985121691585518265221317120785 | 191 |
UVM_ERROR @ 1016387693 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 1016387693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 61465756784787680446707782924162201274442145765810749097017649050104248632020 | 106 |
UVM_ERROR @ 48439964 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 48439964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 16148747540948946824194615155423386470538064086161019390272360705812105546112 | 95 |
UVM_ERROR @ 29933943 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 29933943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 39153813786460119372506004478062885746914857706949595562989775957098862196487 | 93 |
UVM_ERROR @ 427578992 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 427578992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 47562414812436539639050233048659665118708040104115134794472648084684074357682 | 92 |
UVM_ERROR @ 56409492 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 56409492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 38867605355093742668775079516807735652057610314556067386900035082502068449856 | 92 |
UVM_ERROR @ 428347442 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 428347442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 15183613055257617038037408704678539251308514745382980954114366656376694451415 | 95 |
UVM_ERROR @ 115568637 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 115568637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 34902241452044455834833656084102260627838360092619547859983761104813383522688 | 98 |
UVM_ERROR @ 90356206 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 90356206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 98568825427943047019242582875158872933967067961696927683932442912087697684611 | 97 |
UVM_ERROR @ 53304121 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53304121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 31465718884691623517533120808819342894141594390538992154105312217175515384558 | 4037 |
UVM_ERROR @ 11127233583 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 11127233583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 5752094029640871559711706962835420188642705554761306774756985070617742792267 | 101 |
UVM_ERROR @ 104992114 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 104992114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 9766486858648754899599317704247613107031286373288431966769060924066192346275 | 349 |
UVM_ERROR @ 1099998080 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 1099998080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 22654659794003469151036345437262877036358380327314862193671222519684394016184 | 92 |
UVM_ERROR @ 431165980 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 431165980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 71096987364260750357252604818193381742793923253181199630772721484352836271498 | 3668 |
UVM_ERROR @ 1478424559 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 1478424559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 7904161752566961646045893677123263653641795507788113089607470052166818215915 | 92 |
UVM_ERROR @ 435260628 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 435260628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 96945294301101478319799979537794012638352153580314947997752384797653412092544 | 95 |
UVM_ERROR @ 54848800 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 54848800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 82577580864065261470636931416791443879935785442115825715394632241574992621412 | 92 |
UVM_ERROR @ 430121103 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 430121103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 22231653468768867235091081915386905474828151416119231889421331041537951327531 | 93 |
UVM_ERROR @ 429916786 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 429916786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 111782467965641569828160706387253340927861696460309412612147894139952844183847 | 97 |
UVM_ERROR @ 106630034 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 106630034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 49637985004324862932894900689268586363401649033661044621093171609081950357010 | 92 |
UVM_ERROR @ 81574228 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 81574228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 109756390860466861841672346820063029346041278222196367360639234068403948431448 | 93 |
UVM_ERROR @ 428832695 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 428832695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 12967383777470914085479870942494410528899146415942513393634262549352305258409 | 92 |
UVM_ERROR @ 64606206 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 64606206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 47534864751086945638560188453941399762588810665057399843118332872020419647278 | 93 |
UVM_ERROR @ 27363101 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27363101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 86942797932535662119738898510735779668119713474321432810875867796324179507015 | 92 |
UVM_ERROR @ 54319346 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 54319346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 104521723170976661236753086398416510088403100686284248994981671226352194036210 | 101 |
UVM_ERROR @ 453177142 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 453177142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 12517699431278387769331075575357897690266264757156142490335152899560643298896 | 93 |
UVM_ERROR @ 27492428 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27492428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 1373424043439169980739246074994584607638105260587224690745596368101778488804 | 101 |
UVM_ERROR @ 27914031 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27914031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 49109803336762525440301016120176124013443320757214163103029096267037375215908 | 93 |
UVM_ERROR @ 36966321 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 36966321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 31951389534320196818519888534029307793293940517998007293218444110456949133979 | 92 |
UVM_ERROR @ 106533740 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 106533740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 79222983897301364626281872023841518615067456420593467406258267734536507861520 | 217 |
UVM_ERROR @ 66338233 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 66338233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 91286730830287324655704289804903938150637577798909966727579030400276975487030 | 92 |
UVM_ERROR @ 429880739 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 429880739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 86174759794692845182033198301651516778093847022381753314300247807733293982544 | 97 |
UVM_ERROR @ 29069074 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 29069074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 98275957906079215184935915039479627715950702221378633389327583034926119843403 | 95 |
UVM_ERROR @ 36036510 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 36036510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 73934266786464383404537289323851362185067757399295861281058522119127530581358 | 98 |
UVM_ERROR @ 37223904 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 37223904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 9745615730013857985714602057036085009211117857045361427193967078521647480684 | 92 |
UVM_ERROR @ 28192929 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28192929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 92556749352854486937950399096526624891743998270248555768904797846427736152367 | 97 |
UVM_ERROR @ 28882105 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28882105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 44824476311995884092389070300943570928315607746922702257278407147488524179796 | 92 |
UVM_ERROR @ 65620872 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 65620872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 22165664406197763341835712949723333996583835498008348598637389790634652614541 | 92 |
UVM_ERROR @ 54486654 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 54486654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 75142887433548577228021616550889185242431523980452877190519306354601219651556 | 92 |
UVM_ERROR @ 429414559 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 429414559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 86137646043559959183256926533322388405807991432912739513062400892212023456620 | 92 |
UVM_ERROR @ 58006356 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 58006356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 18150922846605449933254289910754595421876721767553376215374698356748560668402 | 95 |
UVM_ERROR @ 28670412 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28670412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 65000897098770619954757646524399627240196939071050988169214675108068250683950 | 95 |
UVM_ERROR @ 75276200 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 75276200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 14054442723259710137881551036350194336796438753355950383770170346126353072901 | 98 |
UVM_ERROR @ 28501458 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28501458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 37949971873499979446654438085429876565984392278759006379330281851213940656628 | 101 |
UVM_ERROR @ 109121473 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 109121473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 110516039368366756808835722499868247297751545267217763728384442834985641918624 | 92 |
UVM_ERROR @ 107018475 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 107018475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 97775780022359175123775139328100931658248237694137751642381981252389580753042 | 157 |
UVM_ERROR @ 87411335 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 87411335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 12086705346806209876286444021216865439167250071872676412806728310464025820187 | 92 |
UVM_ERROR @ 29468990 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 29468990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 49302395752515372293821284427607938321201272780951346963016027357055953550446 | 93 |
UVM_ERROR @ 65448114 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 65448114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 89969756049333857156032235744197883017809379187490930865332552107167011048566 | 99 |
UVM_ERROR @ 26984926 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26984926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 71125665161429755941000083309636171031656968152100930271333622331496426970764 | 99 |
UVM_ERROR @ 435507114 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 435507114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 70971901523210080146036717203270557025087049407759529169857272349898928319034 | 95 |
UVM_ERROR @ 53363689 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53363689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 35602699886613235237587278435363082624528954943895977386845443954541811869833 | 93 |
UVM_ERROR @ 433897636 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 433897636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 29635565311636604495210128246058337339594018043702157705248961789632155515581 | 93 |
UVM_ERROR @ 27470638 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27470638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 111149453867139236254806429397145596864199255486711868766727367653666294154586 | 92 |
UVM_ERROR @ 107348383 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 107348383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 27139980830276602395927193308451637235826327481147842596498060433557703879333 | 387 |
UVM_ERROR @ 79860103 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 79860103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 52179043259072277018944591774924849850464659587908241469721293972928526856822 | 99 |
UVM_ERROR @ 55706789 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 55706789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 69990872923081377709930030732674131175985995358679751234050197039984265890694 | 223 |
UVM_ERROR @ 2299833619 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 2299833619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 60160714764971055909426116432770599175355506939543270120595569218623903019424 | 92 |
UVM_ERROR @ 36823420 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 36823420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 107675560063868109129578917323377564101235517009560957938626257398854460120406 | 92 |
UVM_ERROR @ 112685217 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 112685217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 114355401414816108341547950592823522636363651682686715218647318869561436916044 | 92 |
UVM_ERROR @ 112215577 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 112215577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 25753784217202509864657542540894469134139314654184024573875005267544439470260 | 92 |
UVM_ERROR @ 82801386 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 82801386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 72818856842465302454191042993598340219805733474264262516567227319213254218262 | 99 |
UVM_ERROR @ 28327340 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28327340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 75211396541003404763277983165966840151096246368650761847793716639568449766880 | 92 |
UVM_ERROR @ 33041293 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 33041293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 90340880159088816992523826433740209555519107369827457661445137629142900014433 | 93 |
UVM_ERROR @ 28908899 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28908899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 3952463326056287666711383017209106160350123348358992718420152173093073448546 | 95 |
UVM_ERROR @ 66551426 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 66551426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 61903339766346966134550338486819413832480875054000452813261635485705959419962 | 95 |
UVM_ERROR @ 29236957 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 29236957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 94836373778615287323502256775389120820075034305954675365766494091978070348619 | 226 |
UVM_ERROR @ 720449521 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 720449521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 84442514651853720771122257048911218112254907876554714709397021370425546206011 | 1134 |
UVM_ERROR @ 830014875 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 830014875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 51596066997484647130184498297800620621140773976254380219543068819687172080110 | 93 |
UVM_ERROR @ 64832560 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 64832560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 83642089180562552905682105056731812100997961800188621309787414331204060127280 | 99 |
UVM_ERROR @ 436704373 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 436704373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 31196307455116947788381549452091481775407328773924774072078434364050844791168 | 107 |
UVM_ERROR @ 469196116 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 469196116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 49668220408405389843609252060759430962497974978148850336801156500521576057399 | 105 |
UVM_ERROR @ 436133752 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 436133752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 27900357123012436790256065497512481934221588521071054802596801822896451943369 | 93 |
UVM_ERROR @ 30201482 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 30201482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 8917276087759289968432625743734532166337121418824623035189364331053874505506 | 92 |
UVM_ERROR @ 450909298 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 450909298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 50594180496539362756860486165598350970955804697617414653483305564369516586729 | 92 |
UVM_ERROR @ 56867713 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 56867713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 106496468945481000644364754888123454383109953372441070904277494646427242963485 | 97 |
UVM_ERROR @ 105646616 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 105646616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 58395500364584432536625980079304374062321455847866593748586874864193336185011 | 93 |
UVM_ERROR @ 433954058 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 433954058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 87998683185173256428903157967160175328269338447536260477860050422439850992963 | 97 |
UVM_ERROR @ 33625631 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 33625631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 10056844778108104413266494846484162696373243342644418778839270288169058780864 | 178 |
UVM_ERROR @ 88807411 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 88807411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 14998834616181886491076355710961904723535581241281731028588093023881202648773 | 92 |
UVM_ERROR @ 58432552 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 58432552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(cio_test_en_o == *)' | ||||
| otp_ctrl_csr_mem_rw_with_rand_reset | 110508993537144012780003843910504961227898704920039455515543414249720686161472 | 99 |
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 64093085 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 64093085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 97684236111153784435490381818265388182605040421193544555831796003328508962404 | 93 |
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 53396445 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 53396445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 61036101911396179484450611354120553500936843707088088745968513328244942083981 | 93 |
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 107162314 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 107162314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 447473511875232343255611989054595993701874386743543967467325068263576057753 | 93 |
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 31571560 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 31571560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* | ||||
| otp_ctrl_check_fail | 40343164398114241170081976982986603976510158467397331538152925796012886813968 | 719 |
UVM_ERROR @ 106383682 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 106383682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 45281307751034164972578517043814092184331030363665143915432708233718858115553 | 157 |
UVM_ERROR @ 219816126 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 219816126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 32908622693316173280975198183812567619407556058573963279983050527212399979436 | 1005 |
UVM_ERROR @ 57277954 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 57277954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 18445024083615754352360132495918528805506614338292692044285597101639518760330 | 397 |
UVM_ERROR @ 352076986 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 352076986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 103843289650056686144558498425716216628619854964565816503021399829460717557607 | 227 |
UVM_ERROR @ 92431195 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1156029852 [0x44e79d9c] vs 1156025756 [0x44e78d9c]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 92431195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 79539349735530665120025782671872496948401443921309029861580693952402855635492 | 6494 |
UVM_ERROR @ 3106053776 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8192 [0x2000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3106053776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 102801908303926836414850625524916010239357548020225623790276520490115300515438 | 2100 |
UVM_ERROR @ 633379551 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2 [0x2]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 633379551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 87982271931964559459001074232576245584848375743607652571720578658885205576542 | 2209 |
UVM_ERROR @ 130573088 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1291793875 [0x4cff35d3] vs 1291793872 [0x4cff35d0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 130573088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 16672074712864517314545444154720059145448393916044625008481113726657458583360 | 959 |
UVM_ERROR @ 303378428 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 303378428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 18650873513772542092541931715885869649749422791244098827928267112524555970183 | 2031 |
UVM_ERROR @ 87999039 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2498089709 [0x94e5d2ed] vs 2498089701 [0x94e5d2e5]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 87999039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 84916276005751516760149214480430499115048589843023305604275522099822431239189 | 12234 |
UVM_ERROR @ 9356183373 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3619000562 [0xd7b590f2] vs 3618967794 [0xd7b510f2]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 9356183373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 43736995104266111939338796255494403390832161859217178497854941625019525467832 | 22484 |
UVM_ERROR @ 870839873 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3757047803 [0xdfeffffb]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 870839873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 15713190951614345231851118216963645135754597303468566362793417872209613966522 | 3025 |
UVM_ERROR @ 522359633 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1024 [0x400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 522359633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 36566858712034969673947454049754038082217314985347732077137656360604110318367 | 1313 |
UVM_ERROR @ 123979500 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 123979500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 64283762068507336303139851946485819084970729076907332574823448282996057992024 | 453 |
UVM_ERROR @ 66206236 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1127432267 [0x4333404b]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 66206236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 111135770692364270602892948630737753339082218973436562540489915216390812424596 | 5016 |
UVM_ERROR @ 5003410638 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 5003410638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 1961096461276296787856241038820861904682485916880440912084019872483230499395 | 657 |
UVM_ERROR @ 341579234 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 341579234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 4383388451215667084663569268385515503514794445780890098649880591331456413389 | 275 |
UVM_ERROR @ 35892641 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 35892641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 4018872755189187875566423849921376945883532945309994012135023464117622884608 | 5996 |
UVM_ERROR @ 252345947 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 252345947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 12200618238582295834329332938649609657861359453098152903380871263870597628674 | 8124 |
UVM_ERROR @ 207010354 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3398835334 [0xca961c86] vs 3398868102 [0xca969c86]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 207010354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 14553853743922254365507737367899074833195850766816207344691030980617821502188 | 1769 |
UVM_ERROR @ 248709024 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2587064847 [0x9a337a0f] vs 2587065871 [0x9a337e0f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 248709024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 56263146758532659987919583675767080420216885693248887882202149671219710943334 | 917 |
UVM_ERROR @ 156148452 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8192 [0x2000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 156148452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 19818094439544580559105720467695074244994241713371764124922707706224942939687 | 327 |
UVM_ERROR @ 141111498 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3040130962 [0xb534b792] vs 3040097682 [0xb5343592]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 141111498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 11563764588143926610301993650076789320803767501582682622675815084054798104591 | 4218 |
UVM_ERROR @ 254486124 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (136918120 [0x8293468] vs 136909928 [0x8291468]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 254486124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 76999939607325613375442983370331771987327154505524223662103534060631147039150 | 2413 |
UVM_ERROR @ 402814122 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (718511261 [0x2ad39c9d] vs 718511519 [0x2ad39d9f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 402814122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 103406430984978041377966798654535746570867421720476152042419056317889346147857 | 313 |
UVM_ERROR @ 174050596 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2048 [0x800]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 174050596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 101387463204368868789385564432650310986254534052642352526072189320101266875819 | 15601 |
UVM_ERROR @ 1567984296 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1125090506 [0x430f84ca] vs 1125106890 [0x430fc4ca]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1567984296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 24712117900626624642196968758609806971286871982550679971343171721770231362842 | 2365 |
UVM_ERROR @ 541140523 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 541140523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_dai_errs | 66014928702655697994065444533175870267184050262401670721300651081730710612449 | 1175 |
UVM_ERROR @ 465546371 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3774842827 [0xe0ff87cb] vs 4278190043 [0xfeffffdb]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 465546371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 91883069198142132788033693320714023876825037027160579051971819546935285038151 | 1989 |
UVM_ERROR @ 106513258 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2301345925 [0x892bc085]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 106513258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 4186988028311421798822408319283030769319359842546824551749090547522430902079 | 37691 |
UVM_ERROR @ 5150835371 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1934970616 [0x73554ef8] vs 4151795452 [0xf7775efc]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 5150835371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 18889841308096792019520268933501126396410205991964507229914362074033152768642 | 6235 |
UVM_ERROR @ 625347637 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 625347637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 99244649554640458173773577425681832346506526917371391046693691752224769143478 | 1924 |
UVM_ERROR @ 1631883620 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3663929182 [0xda631f5e] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_1
UVM_INFO @ 1631883620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 97837801463759215470825065358939052975006810613244262523016792696695676415901 | 1245 |
UVM_ERROR @ 742149078 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 742149078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 4018521229366143942460172537371091355364372201899550679562700148514442418748 | 8274 |
UVM_ERROR @ 15081153454 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4047532665 [0xf1407279] vs 4047534717 [0xf1407a7d]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 15081153454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 21698505996525285138146447567322426900491771298103038288549302885892093810183 | 1571 |
UVM_ERROR @ 369008125 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (127760549 [0x79d78a5] vs 127760565 [0x79d78b5]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 369008125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 74807903476754109991890933835136505964888192267324388427469197889082121790055 | 117 |
UVM_ERROR @ 456040283 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 48 [0x30]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 456040283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 89426443419945765595462612802262303883011097051783091533615259431179911583088 | 761 |
UVM_ERROR @ 1093831646 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1093831646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 108983353222412401710682440737385760273799185619666220800869070788994231669285 | 527 |
UVM_ERROR @ 291956294 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2048 [0x800]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 291956294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 30702715997767051190107922081884713901233448271951034301219002499719392892636 | 9153 |
UVM_ERROR @ 9681908783 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (974911841 [0x3a1bf961] vs 974879073 [0x3a1b7961]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 9681908783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 76115162762764927864445310218064221509559586693946198419342630130943695774551 | 5301 |
UVM_ERROR @ 1061842654 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1061842654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 59655601534246216278754031753892171995852418464303687730903275279368475707216 | 1711 |
UVM_ERROR @ 300209641 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 300209641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 91978043175226345132376888604791987944328328391388953288946627563555968136744 | 759 |
UVM_ERROR @ 182409845 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2038916592 [0x798765f0] vs 2038916593 [0x798765f1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 182409845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 13080531546361059362972132981189667123004920008073100947463199335318457698216 | 9546 |
UVM_ERROR @ 2848176788 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 528 [0x210]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2848176788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 70326459690210225914795691477338885661182242128514241396934483383999768433424 | 2350 |
UVM_ERROR @ 1112065840 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2781229411 [0xa5c63163] vs 2781229410 [0xa5c63162]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1112065840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 39903010343793138963582629795325264619566002500166599606438690142214029721183 | 16744 |
UVM_ERROR @ 362729882 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2146893823 [0x7ff6ffff]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 362729882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 41163048303407644306114926114155143230024000050663746026381439660413565411063 | 10137 |
UVM_ERROR @ 9381021889 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2514892418 [0x95e63682] vs 2514892419 [0x95e63683]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 9381021889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 32214807664354708158663017215071477953914607344464304648166974462296446610808 | 2128 |
UVM_ERROR @ 455731216 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2890854101 [0xac4eeed5] vs 2890858197 [0xac4efed5]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 455731216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 112884198948680466319806139666160153079255886865399826019630406461610152617123 | 2878 |
UVM_ERROR @ 4980571169 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 9 [0x9]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 4980571169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 17088034515185894451101810987896646874750898332313115498491026953731403591809 | 1383 |
UVM_ERROR @ 1442961408 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2974225438 [0xb147141e] vs 2974225470 [0xb147143e]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1442961408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 43352901815862675636925308058947566399548374666683209862949377852517176954907 | 3095 |
UVM_ERROR @ 5385271967 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8194 [0x2002]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 5385271967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 23215938998137284790306178390380802649899707756204184449997054477474889495019 | 28525 |
UVM_ERROR @ 10408597934 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4160741231 [0xf7ffdf6f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 10408597934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 22329855185880901857736896646650061297636400574839222205082263073359325658677 | 335 |
UVM_ERROR @ 549914474 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2332261057 [0x8b037ac1] vs 2332262083 [0x8b037ec3]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 549914474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 11873656150853317176162271380612953343213990672439747547711570388557737278055 | 2888 |
UVM_ERROR @ 217466931 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3905798804 [0xe8cdc294] vs 3905802900 [0xe8cdd294]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 217466931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 82765491220317655919279478474844000968718033725441539541044826179134972447851 | 2001 |
UVM_ERROR @ 766895430 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16400 [0x4010]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 766895430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 90182542321029192279668319717662980612564923643981318149082896237078368708713 | 655 |
UVM_ERROR @ 117796033 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 117796033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 40075526649569385546852439569471584973331439945111595236633865883615633683495 | 2884 |
UVM_ERROR @ 175917646 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 175917646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 56866230007166605397187370171275638441823631832487106635839213304904701012537 | 1931 |
UVM_ERROR @ 340209481 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1024 [0x400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 340209481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 76136373975727076442936766954386483772178641569308148770444818151625653577723 | 845 |
UVM_ERROR @ 195417616 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 195417616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 71570712615115710525466071693983537702247329987091958412892530610485421162639 | 5272 |
UVM_ERROR @ 1179980726 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1539854069 [0x5bc84ef5] vs 1539853045 [0x5bc84af5]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1179980726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 71125572342849707151972531597724134141804504774743243283887293982464232429766 | 1477 |
UVM_ERROR @ 46397990 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 46397990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_dai_errs | 66388173989937824718766301214091834942352208020079852969924466635756760338823 | 843 |
UVM_ERROR @ 211900676 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1006862880 [0x3c038220] vs 4282897976 [0xff47d638]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 211900676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 35529263310857640451216600012108022281228779045158438627477962653903411024239 | 1706 |
UVM_ERROR @ 132709078 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8192 [0x2000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 132709078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 14320443071386073933038974975166671128330356269808643163726685485842299695954 | 4110 |
UVM_ERROR @ 228850591 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 228850591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 17484361676078337686829534055209718141283769468921548724836302800606884677219 | 25781 |
UVM_ERROR @ 46509984148 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 46509984148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 30444729350639483227305167096696537634155606182890272233132194800595191336241 | 4523 |
UVM_ERROR @ 462129982 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 462129982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 65468785149782117234429368117873007327472164781115982039896707583281320481573 | 24435 |
UVM_ERROR @ 18369500044 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (966904703 [0x39a1cb7f] vs 2074467327 [0x7ba5dbff]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 18369500044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 39796458619589095225854323152871931442930653789940571228594229740495449023075 | 1469 |
UVM_ERROR @ 248537414 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (384691850 [0x16edee8a] vs 384691914 [0x16edeeca]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 248537414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 66719473943836719563373925499427185200130778827526377053537870631865202842384 | 1999 |
UVM_ERROR @ 57968647 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 57968647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 88651705728707897651386879239118098577468749741117808314140170680231623569892 | 2676 |
UVM_ERROR @ 131592959 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 131592959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 10076805333096745320868171274704047051757272109589062408531559786970924953531 | 2748 |
UVM_ERROR @ 4413809132 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8704 [0x2200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 4413809132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 31089343339525832318941267276248941845783843703494270475278835888843207457523 | 3632 |
UVM_ERROR @ 314688906 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2871786917 [0xab2bfda5] vs 2871786933 [0xab2bfdb5]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 314688906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 74373950527650569193012419316035411899421967036861155002250658206291577876209 | 747 |
UVM_ERROR @ 139856597 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 139856597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! | ||||
| otp_ctrl_stress_all | 78015734644006760045730042533595645143607703924989147651088935526302455076283 | 62728 |
UVM_ERROR @ 35273889044 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 35273889044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 17393510380955587531981340250500268375672267420966674923317140515582280542051 | 53643 |
UVM_ERROR @ 36964434775 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 36964434775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 2853566383739570889516431275793502807278505944113126142897668885781519996345 | 22582 |
UVM_ERROR @ 5729613559 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 5729613559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 160815167460144792647103316168252522682582509834960824077308363414881425137 | 13547 |
UVM_ERROR @ 6451075538 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 6451075538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 10480381664405291020282208148138227961022598364700150760374482775686010336540 | 1801 |
UVM_ERROR @ 171225496 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 171225496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 50371230815090775983648698573303603679105025996808695323920648710001135990143 | 4996 |
UVM_ERROR @ 1570763519 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1570763519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 71893566768201094917629162520531439672800671992042865081521986902488515821755 | 12570 |
UVM_ERROR @ 882821467 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 882821467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 95579686694557601555326492941439548537981586924120704731673122765951017750752 | 60140 |
UVM_ERROR @ 29630302506 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 29630302506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 44956261013407366804460750977283988290361287630264812909166243201864682889406 | 40942 |
UVM_ERROR @ 46300706668 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 46300706668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 68595435832150364555964309532181765801276553122263037953731365813237334093531 | 24325 |
UVM_ERROR @ 1742303286 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1742303286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 36009766642271255577332851376125284789812860081380757131209556588626895933367 | 147073 |
UVM_ERROR @ 10223571237 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 10223571237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 34502619535397844928741124720565316864361664966843514858120584743530446495666 | 73336 |
UVM_ERROR @ 13331951997 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 13331951997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 104031330201762131727862010603172273575082995161114921247005631377437216353177 | 69603 |
UVM_ERROR @ 68569779549 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 68569779549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 99143811906783331452818561629124285959553190191301502499934640879409817410242 | 19207 |
UVM_ERROR @ 1011121474 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1011121474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 51788957674982772429616811062201173448797136693660998599195420674268827298418 | 26563 |
UVM_ERROR @ 33880328902 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 33880328902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 2125967266654406003963148370911911458082523853814753052085823746834306398412 | 22685 |
UVM_ERROR @ 28102278275 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 28102278275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 109095396729894676739309391966784156893774250804177330243714850212976735139041 | 45819 |
UVM_ERROR @ 25868188482 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 25868188482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire | ||||
| otp_ctrl_sec_cm | 61506274372801428023329792932217216825936433573955169509571366998702686521505 | 2552 |
UVM_ERROR @ 146625279371 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 146625279371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_sec_cm | 48910729967920605488985597588151480078319432462775797937394269686004999431588 | 1835 |
UVM_ERROR @ 14058559018 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 14058559018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! | ||||
| otp_ctrl_init_fail | 108867630046625167928404153422736795904444744518127696288486730749734263664306 | 1297 |
UVM_ERROR @ 314140310 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 314140310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 74911944324578875254218705758775963154887886039710632963378274003469599439558 | 1919 |
UVM_ERROR @ 862653069 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 862653069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 46659353588798678304718284017037303103721663532201049633532363234484678794220 | 1405 |
UVM_ERROR @ 371930790 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 371930790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 24136716429676324766063840812475745099165110286442581085700661004466695996937 | 1637 |
UVM_ERROR @ 1743427803 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1743427803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 103423184960826235852330081937924727708194290530920256229807078022417352894892 | 1669 |
UVM_ERROR @ 1512955173 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1512955173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 102648464659902506969720204168418875021871606791955944019111764766481500820545 | 1789 |
UVM_ERROR @ 1825097094 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1825097094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 109619602492537004553703676088177881539343063379969252453625392883441149243551 | 1835 |
UVM_ERROR @ 88383507 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 88383507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 89744548712409434584620045979840864473966208405295349991801651586666258336578 | 1407 |
UVM_ERROR @ 234676277 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 234676277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 21719873515667661904390956384055850853463022082904171015368441007632869862871 | 2153 |
UVM_ERROR @ 1886582932 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1886582932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 111188772897941170802401130712293091030786012496431675772529244651554180335815 | 3539 |
UVM_ERROR @ 1226547788 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1226547788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 3723349493373863037016867298589168698757946744301706618778291588424586737095 | 1391 |
UVM_ERROR @ 1266799148 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1266799148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 62314544657583889207829946918358578261135232441946023295118311650592733004138 | 1607 |
UVM_ERROR @ 521033363 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 521033363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 53586350771433310738998059784670905238923036096542207671510069834428329990158 | 1361 |
UVM_ERROR @ 206438098 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 206438098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 28384353790843330135893182833431585280031296160076490538778201766250277932185 | 1753 |
UVM_ERROR @ 260523850 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 260523850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:* | ||||
| otp_ctrl_macro_errs | 3312505173223060763023967583630851039087976464964440700221694565626448808812 | 195 |
UVM_ERROR @ 242052854 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 242052854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 67754181797266579494645977365249296026626166215986677277985133349269534677223 | 6482 |
UVM_ERROR @ 1875619524 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 1875619524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state | ||||
| otp_ctrl_macro_errs | 44833731488904427913764380811920229557521722237381842556017364174050831006728 | 4625 |
UVM_ERROR @ 319941581 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 319941581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 73933430850596275592393557878856448952997510891583238267128413897925599080133 | 2860 |
UVM_ERROR @ 1840858933 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1840858933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 106742767948526039719343262844814874230175559844177760211323725669281279017368 | 4067 |
UVM_ERROR @ 750440140 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 750440140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * | ||||
| otp_ctrl_check_fail | 54574361686993997775202676153996320832505938285892846314130677773063652319266 | 8745 |
UVM_ERROR @ 1630520039 ps: (otp_ctrl_scoreboard.sv:958) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (259 [0x103] vs 257 [0x101]) reg name: status, compare_mask 0
UVM_INFO @ 1630520039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|