Simulation Results: rom_ctrl/32kb

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
90.57%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 8.060s 0.000us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 9.330s 0.000us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 6.310s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.830s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 8.130s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.900s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 6.310s 0.000us 20 20 100.00
rom_ctrl_csr_aliasing 8.130s 0.000us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 5.790s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.830s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 4.260s 0.000us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 26.660s 0.000us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 10.960s 0.000us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 9.100s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 12.370s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 12.370s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.330s 0.000us 5 5 100.00
rom_ctrl_csr_rw 6.310s 0.000us 20 20 100.00
rom_ctrl_csr_aliasing 8.130s 0.000us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.330s 0.000us 5 5 100.00
rom_ctrl_csr_rw 6.310s 0.000us 20 20 100.00
rom_ctrl_csr_aliasing 8.130s 0.000us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.910s 0.000us 17 20 85.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.050s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 236.860s 0.000us 5 5 100.00
rom_ctrl_tl_intg_err 62.990s 0.000us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 236.860s 0.000us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 236.860s 0.000us 5 5 100.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.910s 0.000us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.910s 0.000us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.910s 0.000us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.910s 0.000us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.910s 0.000us 17 20 85.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 236.860s 0.000us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 236.860s 0.000us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 8.060s 0.000us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 8.060s 0.000us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 8.060s 0.000us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 62.990s 0.000us 20 20 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 136.910s 0.000us 17 20 85.00
rom_ctrl_kmac_err_chk 10.960s 0.000us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.910s 0.000us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.910s 0.000us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 136.910s 0.000us 17 20 85.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.050s 0.000us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 236.860s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 468.050s 0.000us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 80741449746191665662568663186296822848515630231432597691798725274190886192 106
UVM_ERROR @ 1269502090 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1269502090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 113763419112707023413203109023159368182387320087262938528104365561553894768297 95
UVM_ERROR @ 5744967346 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 5744967346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 9204929769019269087667704109113572886418244563461778925661962738401665679667 102
UVM_ERROR @ 1447999643 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1447999643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---