Simulation Results: spi_device/2p

 
29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.08 %
  • code
  • 94.28 %
  • assert
  • 94.74 %
  • func
  • 99.21 %
  • line
  • 99.16 %
  • branch
  • 98.49 %
  • cond
  • 96.65 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
99.29%
V2
99.95%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
spi_device_flash_and_tpm 467.800s 0.000us 49 50 98.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.540s 0.000us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 2.830s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 23.590s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 16.160s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 3.350s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 2.830s 0.000us 20 20 100.00
spi_device_csr_aliasing 16.160s 0.000us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 0.990s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 2.390s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.180s 0.000us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.460s 0.000us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.720s 0.000us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 8.980s 0.000us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 8.980s 0.000us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 23.700s 0.000us 50 50 100.00
spi_device_tpm_sts_read 1.390s 0.000us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 38.770s 0.000us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 22.690s 0.000us 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 34.140s 0.000us 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 34.140s 0.000us 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 27.450s 0.000us 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 27.450s 0.000us 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 27.450s 0.000us 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 27.450s 0.000us 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 27.450s 0.000us 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
flash_cmd_upload 50 50 100.00
spi_device_upload 57.110s 0.000us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 212.860s 0.000us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 212.860s 0.000us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 212.860s 0.000us 50 50 100.00
cmd_read_buffer 100 100 100.00
spi_device_flash_mode 43.080s 0.000us 50 50 100.00
spi_device_read_buffer_direct 19.670s 0.000us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 212.860s 0.000us 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 235.790s 0.000us 50 50 100.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 22.260s 0.000us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 22.260s 0.000us 50 50 100.00
TPM_with_flash_or_passthrough_mode 49 50 98.00
spi_device_flash_and_tpm 467.800s 0.000us 49 50 98.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 417.850s 0.000us 50 50 100.00
stress_all 50 50 100.00
spi_device_stress_all 400.390s 0.000us 50 50 100.00
alert_test 50 50 100.00
spi_device_alert_test 1.150s 0.000us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.100s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 4.690s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 4.690s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.540s 0.000us 5 5 100.00
spi_device_csr_rw 2.830s 0.000us 20 20 100.00
spi_device_csr_aliasing 16.160s 0.000us 5 5 100.00
spi_device_same_csr_outstanding 4.600s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.540s 0.000us 5 5 100.00
spi_device_csr_rw 2.830s 0.000us 20 20 100.00
spi_device_csr_aliasing 16.160s 0.000us 5 5 100.00
spi_device_same_csr_outstanding 4.600s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_tl_intg_err 21.550s 0.000us 20 20 100.00
spi_device_sec_cm 1.590s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 21.550s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
spi_device_flash_mode_ignore_cmds 341.410s 0.000us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *
spi_device_flash_and_tpm 16441581044348304242512383732297964180060882281034759890316508664931573967916 93
UVM_ERROR @ 997737868 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (9852928 [0x965800] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x965800 != exp 0x0
tl_ul_fuzzy_flash_status_q[i] = 0x663db0
tl_ul_fuzzy_flash_status_q[i] = 0xe7676e
UVM_INFO @ 1035102618 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/8
UVM_INFO @ 1035102618 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 5/8