Simulation Results

Simulation Results: spi_host

29/03/2026 00:12:07 DVSim: v1.16.0 sha: 34fa6f9 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.81 %

code
95.03 %

assert
95.64 %

func
90.76 %

block
96.96 %

line
98.76 %

branch
93.35 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.91%
V2S		100.00%
unmapped		80.00%

140/140 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	113.000s	0.000us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	29.000s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	29.000s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	25.000s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	22.000s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	8.000s	0.000us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	29.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	22.000s	0.000us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	29.000s	0.000us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	29.000s	0.000us	5	5	100.00

1139/1140 passed

99.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	2.000s	0.000us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	47.000s	0.000us	50	50	100.00
	spi_host_error_cmd	2.000s	0.000us	50	50	100.00
	spi_host_event	495.000s	0.000us	50	50	100.00
clock_rate				50	50	100.00
	spi_host_speed	12.000s	0.000us	50	50	100.00
speed				50	50	100.00
	spi_host_speed	12.000s	0.000us	50	50	100.00
chip_select_timing				50	50	100.00
	spi_host_speed	12.000s	0.000us	50	50	100.00
sw_reset				50	50	100.00
	spi_host_sw_reset	194.000s	0.000us	50	50	100.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	2.000s	0.000us	50	50	100.00
cpol_cpha				50	50	100.00
	spi_host_speed	12.000s	0.000us	50	50	100.00
full_cycle				50	50	100.00
	spi_host_speed	12.000s	0.000us	50	50	100.00
duplex				50	50	100.00
	spi_host_smoke	113.000s	0.000us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	113.000s	0.000us	50	50	100.00
stress_all				50	50	100.00
	spi_host_stress_all	82.000s	0.000us	50	50	100.00
spien				50	50	100.00
	spi_host_spien	349.000s	0.000us	50	50	100.00
stall				49	50	98.00
	spi_host_status_stall	1392.000s	0.000us	49	50	98.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	27.000s	0.000us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	47.000s	0.000us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	2.000s	0.000us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	29.000s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	30.000s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	30.000s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	29.000s	0.000us	5	5	100.00
	spi_host_csr_rw	29.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	22.000s	0.000us	5	5	100.00
	spi_host_same_csr_outstanding	8.000s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	29.000s	0.000us	5	5	100.00
	spi_host_csr_rw	29.000s	0.000us	20	20	100.00
	spi_host_csr_aliasing	22.000s	0.000us	5	5	100.00
	spi_host_same_csr_outstanding	8.000s	0.000us	20	20	100.00

V2S

45/45 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_tl_intg_err	30.000s	0.000us	20	20	100.00
	spi_host_sec_cm	2.000s	0.000us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	30.000s	0.000us	20	20	100.00

unmapped

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				8	10	80.00
	spi_host_upper_range_clkdiv	589.000s	0.000us	8	10	80.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	spi_host_upper_range_clkdiv	82298676555912007274050925893234480299196154047980027373503575120735644772278	178	UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = ns spi_host_reg_block.status.active (addr=, Comparison=CompareOpEq, exp_data=, call_count=
	spi_host_upper_range_clkdiv	47297211100105351664371117950110502157988243097536287943779628382455154753617	159	UVM_FATAL @ 129865427782 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0x13df9754, Comparison=CompareOpEq, exp_data=0x0, call_count=15 UVM_INFO @ 129865427782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed
	spi_host_status_stall	115731932646154805104723080217069673453597714693712713406290073020043465667715	768	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 511354998 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed UVM_ERROR @ 511354998 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=511355000 ps UVM_INFO @ 511354998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---