Simulation Results: adc_ctrl

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.08 %
  • code
  • 98.09 %
  • assert
  • 95.95 %
  • func
  • 19.19 %
  • line
  • 99.05 %
  • branch
  • 97.77 %
  • cond
  • 93.63 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.81%
V2S
100.00%
V3
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
adc_ctrl_smoke 21.290s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
adc_ctrl_csr_hw_reset 5.040s 0.000us 5 5 100.00
csr_rw 20 20 100.00
adc_ctrl_csr_rw 2.430s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
adc_ctrl_csr_bit_bash 104.370s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
adc_ctrl_csr_aliasing 4.800s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 3.080s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
adc_ctrl_csr_rw 2.430s 0.000us 20 20 100.00
adc_ctrl_csr_aliasing 4.800s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 50 50 100.00
adc_ctrl_filters_polled 1191.040s 0.000us 50 50 100.00
filters_polled_fixed 50 50 100.00
adc_ctrl_filters_polled_fixed 1205.650s 0.000us 50 50 100.00
filters_interrupt 50 50 100.00
adc_ctrl_filters_interrupt 1361.840s 0.000us 50 50 100.00
filters_interrupt_fixed 50 50 100.00
adc_ctrl_filters_interrupt_fixed 1162.330s 0.000us 50 50 100.00
filters_wakeup 50 50 100.00
adc_ctrl_filters_wakeup 1429.970s 0.000us 50 50 100.00
filters_wakeup_fixed 50 50 100.00
adc_ctrl_filters_wakeup_fixed 1584.240s 0.000us 50 50 100.00
filters_both 49 50 98.00
adc_ctrl_filters_both 1343.600s 0.000us 49 50 98.00
clock_gating 42 50 84.00
adc_ctrl_clock_gating 1144.850s 0.000us 42 50 84.00
poweron_counter 50 50 100.00
adc_ctrl_poweron_counter 17.260s 0.000us 50 50 100.00
lowpower_counter 50 50 100.00
adc_ctrl_lowpower_counter 139.660s 0.000us 50 50 100.00
fsm_reset 50 50 100.00
adc_ctrl_fsm_reset 311.730s 0.000us 50 50 100.00
stress_all 49 50 98.00
adc_ctrl_stress_all 5386.540s 0.000us 49 50 98.00
alert_test 50 50 100.00
adc_ctrl_alert_test 2.600s 0.000us 50 50 100.00
intr_test 50 50 100.00
adc_ctrl_intr_test 2.520s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
adc_ctrl_tl_errors 3.810s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
adc_ctrl_tl_errors 3.810s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
adc_ctrl_csr_hw_reset 5.040s 0.000us 5 5 100.00
adc_ctrl_csr_rw 2.430s 0.000us 20 20 100.00
adc_ctrl_csr_aliasing 4.800s 0.000us 5 5 100.00
adc_ctrl_same_csr_outstanding 12.750s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
adc_ctrl_csr_hw_reset 5.040s 0.000us 5 5 100.00
adc_ctrl_csr_rw 2.430s 0.000us 20 20 100.00
adc_ctrl_csr_aliasing 4.800s 0.000us 5 5 100.00
adc_ctrl_same_csr_outstanding 12.750s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
adc_ctrl_sec_cm 20.370s 0.000us 5 5 100.00
adc_ctrl_tl_intg_err 27.980s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
adc_ctrl_tl_intg_err 27.980s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 49 50 98.00
adc_ctrl_stress_all_with_rand_reset 28.520s 0.000us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_clock_gating 89167060339717545937949992728918404339326033212786181726814161090111295687988 325
UVM_ERROR @ 2602023434 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 2602023434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 81327863244812922717581729138829559867392859417787694613635343100142789510222 359
UVM_ERROR @ 333467789381 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 333467789381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 1814663975061573309660697190383273433989502005830266195691129118210994940552 326
UVM_ERROR @ 19428428922 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 19428428922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 78134772639657985737592483496930392729830267920380957366791532454362558055289 359
UVM_ERROR @ 361880246512 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 361880246512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 22418534776210100124790932573629909905883404549117286378294984569309092699475 342
UVM_ERROR @ 179182209189 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 179182209189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 83320405931504840340345864756328474413939772688661974918936644607985477909557 403
UVM_ERROR @ 20602866958 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 20602866958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 23623641638295879795499536086506408831158423270227161950360206530275948698025 342
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 84681151470242871616621671579417839679923478404682532485958637344107300093593 325
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 91427808970931819401602004978770940526363419145975525885064538072539347197856 342
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 51236211831799385830381303598861578492303632067723140599988016376884583921074 357
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 69937990746631142670191127415551990438118142766897475878834066295789288309413 342
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---