Simulation Results

Simulation Results: csrng

05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.35 %

code
96.23 %

assert
95.85 %

func
90.97 %

block
98.59 %

line
99.57 %

branch
96.46 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		94.34%
V2S		99.96%
V3		0.00%

130/130 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	csrng_smoke	30.000s	0.000us	50	50	100.00
csr_hw_reset				5	5	100.00
	csrng_csr_hw_reset	4.000s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	csrng_csr_rw	5.000s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	csrng_csr_bit_bash	47.000s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	csrng_csr_aliasing	5.000s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	csrng_csr_mem_rw_with_rand_reset	4.000s	0.000us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	csrng_csr_rw	5.000s	0.000us	20	20	100.00
	csrng_csr_aliasing	5.000s	0.000us	5	5	100.00

1500/1590 passed

94.34 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	54.000s	0.000us	500	500	100.00
err				500	500	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
cmds				6	50	12.00
	csrng_cmds	2261.000s	0.000us	6	50	12.00
life cycle				6	50	12.00
	csrng_cmds	2261.000s	0.000us	6	50	12.00
stress_all				48	50	96.00
	csrng_stress_all	1060.000s	0.000us	48	50	96.00
intr_test				50	50	100.00
	csrng_intr_test	3.000s	0.000us	50	50	100.00
alert_test				50	50	100.00
	csrng_alert_test	6.000s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	csrng_tl_errors	12.000s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	csrng_tl_errors	12.000s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	csrng_csr_hw_reset	4.000s	0.000us	5	5	100.00
	csrng_csr_rw	5.000s	0.000us	20	20	100.00
	csrng_csr_aliasing	5.000s	0.000us	5	5	100.00
	csrng_same_csr_outstanding	10.000s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	csrng_csr_hw_reset	4.000s	0.000us	5	5	100.00
	csrng_csr_rw	5.000s	0.000us	20	20	100.00
	csrng_csr_aliasing	5.000s	0.000us	5	5	100.00
	csrng_same_csr_outstanding	10.000s	0.000us	20	20	100.00

V2S

10146/10150 passed

99.96 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	csrng_tl_intg_err	12.000s	0.000us	20	20	100.00
	csrng_sec_cm	17.000s	0.000us	5	5	100.00
sec_cm_config_regwen				70	70	100.00
	csrng_csr_rw	5.000s	0.000us	20	20	100.00
	csrng_regwen	19.000s	0.000us	50	50	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	54.000s	0.000us	500	500	100.00
sec_cm_intersig_mubi				48	50	96.00
	csrng_stress_all	1060.000s	0.000us	48	50	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
	csrng_sec_cm	17.000s	0.000us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
	csrng_sec_cm	17.000s	0.000us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
	csrng_sec_cm	17.000s	0.000us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
	csrng_sec_cm	17.000s	0.000us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
	csrng_sec_cm	17.000s	0.000us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	54.000s	0.000us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
sec_cm_constants_lc_gated				48	50	96.00
	csrng_stress_all	1060.000s	0.000us	48	50	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	54.000s	0.000us	500	500	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	csrng_tl_intg_err	12.000s	0.000us	20	20	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
	csrng_sec_cm	17.000s	0.000us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00
	csrng_sec_cm	17.000s	0.000us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	25.000s	0.000us	200	200	100.00
	csrng_err	19.000s	0.000us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	0.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])
	csrng_cmds	51643474757333896737743568225212007725532962415337034351054529657126856303289	130	UVM_FATAL @ 60028859 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 254259282232246226390257259349792345877 [0xbf488e78ae6294501f15daf7011d4f15]) UVM_INFO @ 60028859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	84464525709419798938446454656245940544114478526157417947506522709761927640567	130	UVM_FATAL @ 248351653 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 121831442726464343315466829132225358284 [0x5ba7e1e318e7e2336b99bbb1d584a9cc]) UVM_INFO @ 248351653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	38060033191748226566245203060624045745193521477894710609845991300777281591602	130	UVM_FATAL @ 22247824 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 298026432946851977675919153763557323589 [0xe035cd9ac9b2d8fe4adc6742e3183345]) UVM_INFO @ 22247824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	40105758090748109370589982120162289752777979611204601078232342797874014447133	130	UVM_FATAL @ 67810417 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 92968907517242906702341448338277678950 [0x45f12908a9d2c45222d81882c0a83f66]) UVM_INFO @ 67810417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	49461011420463662465619891332047122668419387243908211338761039562761444734429	130	UVM_FATAL @ 80264294 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 15694735849598380923456769482333732918 [0xbceb23878e8c08085c5a08ccbc9c036]) UVM_INFO @ 80264294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	90312460334490073460964644953585947310530214861657727296181949259537588269959	130	UVM_FATAL @ 724365463 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 154824409678147223270707041782382851249 [0x747a18bf8112b9f9dc1d1c6ae421f4b1]) UVM_INFO @ 724365463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	90542669856965538253748200265063636535771684890986671538012285958621612567874	130	UVM_FATAL @ 34104948 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 269695407511029652120073958053807959946 [0xcae57234d97fedb426eab47ed0e0af8a]) UVM_INFO @ 34104948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	68863030847705926023089330364792070427358498859267950274533525833340576514999	130	UVM_FATAL @ 118681289 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 323768273124912983856167073826736920914 [0xf39380504e7d7d5e0c036e505cab5952]) UVM_INFO @ 118681289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	65171697527987528463319072425000575936433754808991969034120062230798758738057	130	UVM_FATAL @ 52751010 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 290670248461510140457544389250919547702 [0xdaad0db52794b5454f6f5c5dc79dc336]) UVM_INFO @ 52751010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	35801970773831786529779674207927185310760703876326570828209520426258180828269	139	UVM_FATAL @ 23126812 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 324022185859068036396540164418646344085 [0xf3c4672d935ae15169d5e748fee88195]) UVM_INFO @ 23126812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	25822411871114179676783967152396276096659154633545711326894428415225923369837	130	UVM_FATAL @ 30319422 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 176828467790108008684203384755894901007 [0x8507ec92b74addd70ae0296c7008590f]) UVM_INFO @ 30319422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	75166732532035509356324172240471980328286769315810791561680546752052215610630	130	UVM_FATAL @ 163707022 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 176983168811284867548815148391834759551 [0x8525b7ec1e1e85037c7e43899c7ab17f]) UVM_INFO @ 163707022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	38837822469112642121533264483664779348674000850282938336542516850103603688898	130	UVM_FATAL @ 30453159 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 281304551475747175967676354678291265133 [0xd3a14931eb4f4113bfaa81e692d5766d]) UVM_INFO @ 30453159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	66722153881957351514970058027841487223349911516756240610303597748095459999593	130	UVM_FATAL @ 42506017 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 31800020771453146209089368063103882603 [0x17ec7612bfc19dfe1c21f3b5e476556b]) UVM_INFO @ 42506017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	37331805605124652123978214263387787986728565094875504169414302358808751569011	140	UVM_FATAL @ 128424323 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 239557900163263157116136059664428278663 [0xb4392c5f9c3511162efcec6fbef1a387]) UVM_INFO @ 128424323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	93761327892171444278217972925001461074824594526712225307509451444694345910899	130	UVM_FATAL @ 554388912 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 251236108346232281683448615531150105593 [0xbd02507daadb3f5c2111475a4c58dbf9]) UVM_INFO @ 554388912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	17661635316061776865711758087624734328248167184537634932003763913218657318206	130	UVM_FATAL @ 632882948 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 115840826206936362730279846239739071946 [0x572621b05ed671230672356e18c84dca]) UVM_INFO @ 632882948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	110539641926368072638526544432139012099808725792034572895557303672146356107031	130	UVM_FATAL @ 77562923 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 16680161252272721002376438858418376460 [0xc8c7b71acda39fec0d29526b3164f0c]) UVM_INFO @ 77562923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	65213003131707236097647022893266797556237168131565836118098868112211485112064	130	UVM_FATAL @ 250572605 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 9434700345876910315920283393704345508 [0x7190ea415dcb98907ff8f8dcf3c3fa4]) UVM_INFO @ 250572605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	58046964461776211855135981978536157072172839953564497633249196041786239884192	130	UVM_FATAL @ 142534339 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 61942511152257065579266596466683028992 [0x2e99b196b52cbf631176268e2dd02600]) UVM_INFO @ 142534339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	19341294786693611457197865574584848130453804362470897288368538468845108323587	130	UVM_FATAL @ 85572149 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 174203979011606788825635138406715539084 [0x830e7749381bae1e5429e6cd9740be8c]) UVM_INFO @ 85572149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	70593611441429279648721896688264150246972659687802898395243576070080106387858	130	UVM_FATAL @ 31818571 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 230165405215756372379564299202112289819 [0xad283e9e8b852fe134f1a4f24e7c7c1b]) UVM_INFO @ 31818571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	36135726255501881953201454229724696075606598233638544854194270908115577321032	130	UVM_FATAL @ 87251036 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 327724790485578504077857482533681136160 [0xf68d7fae2c517ba9a1bcefec6b3e8220]) UVM_INFO @ 87251036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	16121125443146930302331305019810511372523651923233781817739393749732745840681	140	UVM_FATAL @ 351758860 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 227711691754022661214180499075513946262 [0xab4fad349572af9060a7101995039096]) UVM_INFO @ 351758860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	4359417123593445051383112528897470253090771130418888572173077021120604807010	130	UVM_FATAL @ 266214659 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 280416974563243054258775231965446561757 [0xd2f658464af22b75a2669caab2805fdd]) UVM_INFO @ 266214659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	23465196270377782056223997340663315803351572211952171478353054983473764530789	130	UVM_FATAL @ 50526548 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 246625191537119112286338255028924112738 [0xb98a48bd8a59f6d9a36fbd36c13adf62]) UVM_INFO @ 50526548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24804657771142452957220008581642790421201448862950790396911748920502824188430	130	UVM_FATAL @ 11011930 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 243991718170847153480602976926239707982 [0xb78f187a9a5b0aa3d6257dfd0066534e]) UVM_INFO @ 11011930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	35597385901823763052486279481786194367047563339647435789855300551686347247200	130	UVM_FATAL @ 119924986 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 33913999211839536818999854731396271116 [0x19839941e2fc536a5868c0c347664c0c]) UVM_INFO @ 119924986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	53142201432528739276633155093607489478457992744766776610256674358308431335638	130	UVM_FATAL @ 68029928 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 300188748389170861035723472878522747860 [0xe1d63ffca9c10d73ce7c14b20dc64bd4]) UVM_INFO @ 68029928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	17212606093720709885101593118930344684310286977038041209538390995828047931732	130	UVM_FATAL @ 46491426 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 336925665930562766247716416442040737422 [0xfd7985dd173fad166a4bf2ec79525e8e]) UVM_INFO @ 46491426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	10073462124695480886482395761140270694951093015817140343176128641826976764107	130	UVM_FATAL @ 235513797 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 235855030478816493256405448559908175679 [0xb17006cd82dc7064ec1d65ba2a253f3f]) UVM_INFO @ 235513797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	58109437069064444393695976811501922218874903731104985398337844550707897789430	130	UVM_FATAL @ 83655206 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 38040451731490206066481932419414865100 [0x1c9e531301b7f36e108a80e5177fb4cc]) UVM_INFO @ 83655206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60594788896449609183113102276254886553439599056262495963817007546007016699653	130	UVM_FATAL @ 29428051 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 230622609159123039445029253290937079411 [0xad804c839c74e2ef88812e142504d673]) UVM_INFO @ 29428051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48469422297358662834794207673596288078685416648651286974019502780185407907316	130	UVM_FATAL @ 183227910 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 176150374888395587703559898639588085405 [0x84855403081c86b430bba1e8725b4e9d]) UVM_INFO @ 183227910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	25740194749805031135453203696506835798635320371072178055430016479909663295367	130	UVM_FATAL @ 24364549 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 247166474760461074158999570467048015652 [0xb9f288105132a543f117ef810f564724]) UVM_INFO @ 24364549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	3165770783895217383270508556700138349813873419474125826217280241000914101887	130	UVM_FATAL @ 27038779 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 212050161495966707765179652385913008165 [0x9f876025997a2f43d969812e0d197025]) UVM_INFO @ 27038779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	58840153558575562878400039215857214153653329517124194414222690352783050721320	150	UVM_FATAL @ 179055295 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 157480942838630266308680320884744713189 [0x7679b9f1f6be8544d4fa27ad590cf3e5]) UVM_INFO @ 179055295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	94526152363785603692784002745750520505196940917423728175285406171912934471848	130	UVM_FATAL @ 17166485 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 16693918324806765852207233470696543903 [0xc8f21b8579fdfcb3eda9e43c160569f]) UVM_INFO @ 17166485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	76447299260660590533134470208557180714831341735070421369181463810723037244764	130	UVM_FATAL @ 12284398 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 296554878465065647601094758097996637810 [0xdf1a645dfa81ad8ba6b59f595bd26672]) UVM_INFO @ 12284398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	115156269354360914730139394133615802832108298647391907908025667734914187537462	130	UVM_FATAL @ 334245512 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 260904133201597848406304680492508207953 [0xc4484eeb17d26f0ba4fb09e5f5895b51]) UVM_INFO @ 334245512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	96691935828453377327943610267564591544025900747874178332815587390824214471008	130	UVM_FATAL @ 109525188 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 309857816811001967437424432746050163830 [0xe91c71ddbfd4719846e755c4b8711476]) UVM_INFO @ 109525188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	81215620222764016007265384092866421707926949476129467593818224862273438218823	130	UVM_FATAL @ 5949771 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 51010188035505893914870260249685213 [0x9d2ff16f9a7a6c9e2010682346cdd]) UVM_INFO @ 5949771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	csrng_stress_all_with_rand_reset	35371331863606787488385375492989213227658732519982087837982131839567449703414	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	38468756686007457953845345321593569829065133803189352496056992754026770548530	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	12591468926768171574377926293124323104748922875555848060007197659579611246647	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	27278223907558344902542839180456303811277710718441889896227511048897455731244	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	39418454952312878424492266056370300185960754934031486756937803298759343378182	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	18359768050217307085953437132442081962131767362609606504622887634031425893142	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	46206394996026346376151184554884016945150198113596895938537668831404150556301	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	101520231959479045391403818746265545801799221309167087580125966105787413795613	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	61165166543088387056977273411687985737481367728648037893728129727821653990739	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	44322921812029095518509874034627099377134014282985525810749591386449083471519	None	Job timed out after 180 minutes
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq
	csrng_stress_all	42585433769106381281282846504018082815479917724729129129005616981004960250146	149	UVM_ERROR @ 4492357581 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq UVM_INFO @ 4492357581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	95840490006156256639150523369504001691413089055008323006844841205978940770526	133	UVM_ERROR @ 51098916 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq UVM_INFO @ 51098916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits
	csrng_cmds	65668635806164233296719667252417504865999044278654762111910742374440858945721	133	UVM_ERROR @ 1260827696 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1229421002 [0x494779ca] vs 0 [0x0]) reg name: csrng_reg_block.genbits UVM_INFO @ 1260827696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	csrng_cmds	100586862658545606016376507607972286600613315179373939735474059113424849090098	139	UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---