Simulation Results: flash_ctrl

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.02 %
  • code
  • 95.86 %
  • assert
  • 96.76 %
  • func
  • 98.45 %
  • line
  • 96.09 %
  • branch
  • 97.40 %
  • cond
  • 94.83 %
  • toggle
  • 98.46 %
  • FSM
  • 92.52 %
Validation stages
V1
100.00%
V2
99.03%
V2S
99.51%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 174.560s 0.000us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 20.410s 0.000us 5 5 100.00
csr_hw_reset 5 5 100.00
flash_ctrl_csr_hw_reset 32.400s 0.000us 5 5 100.00
csr_rw 20 20 100.00
flash_ctrl_csr_rw 18.590s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
flash_ctrl_csr_bit_bash 64.450s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
flash_ctrl_csr_aliasing 54.220s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 20.050s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
flash_ctrl_csr_rw 18.590s 0.000us 20 20 100.00
flash_ctrl_csr_aliasing 54.220s 0.000us 5 5 100.00
mem_walk 5 5 100.00
flash_ctrl_mem_walk 13.730s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
flash_ctrl_mem_partial_access 13.820s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 21.650s 0.000us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 92.630s 0.000us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 2114.190s 0.000us 3 3 100.00
flash_ctrl_hw_rma_reset 1111.120s 0.000us 20 20 100.00
flash_ctrl_lcmgr_intg 13.870s 0.000us 20 20 100.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 2274.310s 0.000us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 361.590s 0.000us 5 5 100.00
program_reset 30 30 100.00
flash_ctrl_prog_reset 177.820s 0.000us 30 30 100.00
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 3001.280s 0.000us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 113.370s 0.000us 5 5 100.00
rd_buff_eviction_w_ecc 96 100 96.00
flash_ctrl_rw_evict 32.810s 0.000us 38 40 95.00
flash_ctrl_rw_evict_all_en 32.540s 0.000us 38 40 95.00
flash_ctrl_re_evict 36.140s 0.000us 20 20 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 200.410s 0.000us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 200.410s 0.000us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 858.790s 0.000us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 28.310s 0.000us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 785.060s 0.000us 20 20 100.00
error_mp 9 10 90.00
flash_ctrl_error_mp 741.670s 0.000us 9 10 90.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 767.290s 0.000us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1181.920s 0.000us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 13.930s 0.000us 20 20 100.00
read_write_overflow 5 5 100.00
flash_ctrl_oversize_error 184.740s 0.000us 5 5 100.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 23.390s 0.000us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 15.260s 0.000us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 947.490s 0.000us 5 5 100.00
secret_partition 129 130 99.23
flash_ctrl_hw_sec_otp 225.050s 0.000us 50 50 100.00
flash_ctrl_otp_reset 108.480s 0.000us 79 80 98.75
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 2114.190s 0.000us 3 3 100.00
interrupts 99 100 99.00
flash_ctrl_intr_rd 224.010s 0.000us 39 40 97.50
flash_ctrl_intr_wr 85.140s 0.000us 10 10 100.00
flash_ctrl_intr_rd_slow_flash 290.640s 0.000us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 642.760s 0.000us 10 10 100.00
invalid_op 19 20 95.00
flash_ctrl_invalid_op 79.370s 0.000us 19 20 95.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 82.180s 0.000us 5 5 100.00
double_bit_err 35 35 100.00
flash_ctrl_read_word_sweep_derr 20.430s 0.000us 5 5 100.00
flash_ctrl_ro_derr 120.980s 0.000us 10 10 100.00
flash_ctrl_rw_derr 215.380s 0.000us 10 10 100.00
flash_ctrl_derr_detect 154.920s 0.000us 5 5 100.00
flash_ctrl_integrity 479.250s 0.000us 5 5 100.00
single_bit_err 25 25 100.00
flash_ctrl_read_word_sweep_serr 22.270s 0.000us 5 5 100.00
flash_ctrl_ro_serr 136.550s 0.000us 10 10 100.00
flash_ctrl_rw_serr 223.410s 0.000us 10 10 100.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 80.660s 0.000us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 126.540s 0.000us 5 5 100.00
scramble 59 62 95.16
flash_ctrl_wo 231.070s 0.000us 18 20 90.00
flash_ctrl_write_word_sweep 6.940s 0.000us 1 1 100.00
flash_ctrl_read_word_sweep 11.150s 0.000us 1 1 100.00
flash_ctrl_ro 107.460s 0.000us 20 20 100.00
flash_ctrl_rw 517.250s 0.000us 19 20 95.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 40.370s 0.000us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 891.200s 0.000us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 255.400s 0.000us 20 20 100.00
alert_test 50 50 100.00
flash_ctrl_alert_test 14.150s 0.000us 50 50 100.00
intr_test 50 50 100.00
flash_ctrl_intr_test 13.790s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
flash_ctrl_tl_errors 21.590s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
flash_ctrl_tl_errors 21.590s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
flash_ctrl_csr_hw_reset 32.400s 0.000us 5 5 100.00
flash_ctrl_csr_rw 18.590s 0.000us 20 20 100.00
flash_ctrl_csr_aliasing 54.220s 0.000us 5 5 100.00
flash_ctrl_same_csr_outstanding 25.670s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
flash_ctrl_csr_hw_reset 32.400s 0.000us 5 5 100.00
flash_ctrl_csr_rw 18.590s 0.000us 20 20 100.00
flash_ctrl_csr_aliasing 54.220s 0.000us 5 5 100.00
flash_ctrl_same_csr_outstanding 25.670s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 74.110s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 74.110s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 74.110s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 74.110s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 89.150s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
flash_ctrl_tl_intg_err 594.540s 0.000us 20 20 100.00
flash_ctrl_sec_cm 2150.820s 0.000us 5 5 100.00
sec_cm_reg_bus_integrity 20 20 100.00
flash_ctrl_tl_intg_err 594.540s 0.000us 20 20 100.00
sec_cm_host_bus_integrity 20 20 100.00
flash_ctrl_tl_intg_err 594.540s 0.000us 20 20 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 28.140s 0.000us 3 3 100.00
flash_ctrl_wr_intg 12.540s 0.000us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 174.560s 0.000us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 259 260 99.62
flash_ctrl_otp_reset 108.480s 0.000us 79 80 98.75
flash_ctrl_disable 23.390s 0.000us 50 50 100.00
flash_ctrl_sec_info_access 82.650s 0.000us 50 50 100.00
flash_ctrl_connect 15.260s 0.000us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 14.140s 0.000us 5 5 100.00
sec_cm_data_regions_config_regwen 20 20 100.00
flash_ctrl_csr_rw 18.590s 0.000us 20 20 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 74.110s 0.000us 20 20 100.00
sec_cm_info_regions_config_regwen 20 20 100.00
flash_ctrl_csr_rw 18.590s 0.000us 20 20 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 74.110s 0.000us 20 20 100.00
sec_cm_bank_config_regwen 20 20 100.00
flash_ctrl_csr_rw 18.590s 0.000us 20 20 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 74.110s 0.000us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 23.390s 0.000us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 28.140s 0.000us 3 3 100.00
flash_ctrl_access_after_disable 14.300s 0.000us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 24.430s 0.000us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 23.390s 0.000us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 28.310s 0.000us 10 10 100.00
sec_cm_mem_scramble 19 20 95.00
flash_ctrl_rw 517.250s 0.000us 19 20 95.00
sec_cm_mem_integrity 25 25 100.00
flash_ctrl_rw_serr 223.410s 0.000us 10 10 100.00
flash_ctrl_rw_derr 215.380s 0.000us 10 10 100.00
flash_ctrl_integrity 479.250s 0.000us 5 5 100.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 2114.190s 0.000us 3 3 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2150.820s 0.000us 5 5 100.00
sec_cm_phy_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2150.820s 0.000us 5 5 100.00
sec_cm_phy_prog_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2150.820s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2150.820s 0.000us 5 5 100.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 18.350s 0.000us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 3 5 60.00
flash_ctrl_phy_host_grant_err 12.510s 0.000us 3 5 60.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 11.880s 0.000us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2150.820s 0.000us 5 5 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2150.820s 0.000us 5 5 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2150.820s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 27.080s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 461.590s 0.000us 3 3 100.00

Error Messages

   Test seed line log context
UVM_ERROR (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (* [*] vs * [*])
flash_ctrl_error_mp 114478215433511166550820944658656192518512852791639127157548687442160616625075 294
UVM_ERROR @ 2050514.7 ns: (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (0xb4881e7e [10110100100010000001111001111110] vs 0x7dad273f [1111101101011010010011100111111])
UVM_INFO @ 2050514.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: *
flash_ctrl_rw_evict 83389300853215122226352299593381341096303263467912397346896220069884829100704 108
UVM_ERROR @ 41998.7 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 41998.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict 113470451670180157859403965486603211605055165109743005212553903999782647228143 108
UVM_ERROR @ 38151.1 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 38151.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict_all_en 47286348071195923156968518360231679009882782286794555787124897381219845775386 108
UVM_ERROR @ 8796.5 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 8796.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict_all_en 51632234596426069882641867371285347580223490928087107570472938267012124782593 108
UVM_ERROR @ 17228.1 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 17228.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
flash_ctrl_phy_host_grant_err 31626280346052029982261223428228889925550825850908139694468020293177456627111 125
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 6099.0 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 6099.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_phy_host_grant_err 83003447519730143988664383092406028450366696514280117674010952910311947893317 125
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 5581.4 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 5581.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *e3dd_3449f3f5:ffffffff_3449f3f* mismatch!!
flash_ctrl_intr_rd 13879584433144039554288820585730294557313869759438239023689675120418736386371 108
UVM_ERROR @ 258609.2 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 1: obs:exp 4839e3dd_3449f3f5:ffffffff_3449f3f5 mismatch!!
UVM_INFO @ 258609.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
flash_ctrl_wo 83168744565092421196049154999084654431708705604845430930026410607353121844697 None
Job timed out after 60 minutes
flash_ctrl_rw 57659982622515210161719042009450905606345512767437563145580847291400654670450 None
Job timed out after 60 minutes
flash_ctrl_wo 109697816679361245826694236967544899960237351290806002110619667448528299183822 None
Job timed out after 60 minutes
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly
flash_ctrl_invalid_op 63949987898427021557677330055104840749331949277248180675477701232067091863717 2455
UVM_ERROR @ 3741350.4 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 3741350.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'dst_req_o'
flash_ctrl_otp_reset 36530288968308353496417740669964984052831113964358295438114693340580816074235 223
Offending 'dst_req_o'
UVM_ERROR @ 26127.4 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq
UVM_INFO @ 26127.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---