Simulation Results: hmac

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.87 %
  • code
  • 99.25 %
  • assert
  • 97.36 %
  • func
  • 100.00 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 13.140s 0.000us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.380s 0.000us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.300s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 8.470s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.580s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 347.630s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.300s 0.000us 20 20 100.00
hmac_csr_aliasing 7.580s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 82.970s 0.000us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 97.340s 0.000us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 281.000s 0.000us 30 30 100.00
hmac_test_sha384_vectors 553.960s 0.000us 75 75 100.00
hmac_test_sha512_vectors 538.440s 0.000us 75 75 100.00
hmac_test_hmac256_vectors 15.700s 0.000us 50 50 100.00
hmac_test_hmac384_vectors 16.260s 0.000us 60 60 100.00
hmac_test_hmac512_vectors 19.060s 0.000us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 39.300s 0.000us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1146.140s 0.000us 10 10 100.00
error 10 10 100.00
hmac_error 85.530s 0.000us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 93.500s 0.000us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 13.140s 0.000us 10 10 100.00
hmac_long_msg 82.970s 0.000us 10 10 100.00
hmac_back_pressure 97.340s 0.000us 25 25 100.00
hmac_datapath_stress 1146.140s 0.000us 10 10 100.00
hmac_burst_wr 39.300s 0.000us 50 50 100.00
hmac_stress_all 3119.220s 0.000us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 13.140s 0.000us 10 10 100.00
hmac_long_msg 82.970s 0.000us 10 10 100.00
hmac_back_pressure 97.340s 0.000us 25 25 100.00
hmac_datapath_stress 1146.140s 0.000us 10 10 100.00
hmac_wipe_secret 93.500s 0.000us 10 10 100.00
hmac_test_sha256_vectors 281.000s 0.000us 30 30 100.00
hmac_test_sha384_vectors 553.960s 0.000us 75 75 100.00
hmac_test_sha512_vectors 538.440s 0.000us 75 75 100.00
hmac_test_hmac256_vectors 15.700s 0.000us 50 50 100.00
hmac_test_hmac384_vectors 16.260s 0.000us 60 60 100.00
hmac_test_hmac512_vectors 19.060s 0.000us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 13.140s 0.000us 10 10 100.00
hmac_long_msg 82.970s 0.000us 10 10 100.00
hmac_back_pressure 97.340s 0.000us 25 25 100.00
hmac_datapath_stress 1146.140s 0.000us 10 10 100.00
hmac_burst_wr 39.300s 0.000us 50 50 100.00
hmac_error 85.530s 0.000us 10 10 100.00
hmac_wipe_secret 93.500s 0.000us 10 10 100.00
hmac_test_sha256_vectors 281.000s 0.000us 30 30 100.00
hmac_test_sha384_vectors 553.960s 0.000us 75 75 100.00
hmac_test_sha512_vectors 538.440s 0.000us 75 75 100.00
hmac_test_hmac256_vectors 15.700s 0.000us 50 50 100.00
hmac_test_hmac384_vectors 16.260s 0.000us 60 60 100.00
hmac_test_hmac512_vectors 19.060s 0.000us 75 75 100.00
hmac_stress_all 3119.220s 0.000us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 3119.220s 0.000us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.930s 0.000us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.970s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.300s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.300s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.380s 0.000us 5 5 100.00
hmac_csr_rw 1.300s 0.000us 20 20 100.00
hmac_csr_aliasing 7.580s 0.000us 5 5 100.00
hmac_same_csr_outstanding 2.630s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.380s 0.000us 5 5 100.00
hmac_csr_rw 1.300s 0.000us 20 20 100.00
hmac_csr_aliasing 7.580s 0.000us 5 5 100.00
hmac_same_csr_outstanding 2.630s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.140s 0.000us 5 5 100.00
hmac_tl_intg_err 4.980s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.980s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 13.140s 0.000us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.850s 0.000us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 891.130s 0.000us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.400s 0.000us 1 1 100.00