Simulation Results: kmac/masked

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.79 %
  • code
  • 94.39 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 80.99 %
Validation stages
V1
100.00%
V2
99.88%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 85.860s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.520s 0.000us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.380s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 15.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.410s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.330s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.380s 0.000us 20 20 100.00
kmac_csr_aliasing 7.410s 0.000us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.050s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.850s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3429.990s 0.000us 50 50 100.00
burst_write 49 50 98.00
kmac_burst_write 1478.620s 0.000us 49 50 98.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2307.540s 0.000us 5 5 100.00
kmac_test_vectors_sha3_256 2157.630s 0.000us 5 5 100.00
kmac_test_vectors_sha3_384 1583.290s 0.000us 5 5 100.00
kmac_test_vectors_sha3_512 1128.700s 0.000us 5 5 100.00
kmac_test_vectors_shake_128 2446.140s 0.000us 5 5 100.00
kmac_test_vectors_shake_256 2131.950s 0.000us 5 5 100.00
kmac_test_vectors_kmac 3.390s 0.000us 5 5 100.00
kmac_test_vectors_kmac_xof 3.530s 0.000us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 491.430s 0.000us 50 50 100.00
app 50 50 100.00
kmac_app 393.760s 0.000us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 337.020s 0.000us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 427.440s 0.000us 50 50 100.00
error 50 50 100.00
kmac_error 450.690s 0.000us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 15.620s 0.000us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.140s 0.000us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 56.710s 0.000us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 55.510s 0.000us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 58.780s 0.000us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 22.000s 0.000us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2053.150s 0.000us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.260s 0.000us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.340s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.830s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.830s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.520s 0.000us 5 5 100.00
kmac_csr_rw 1.380s 0.000us 20 20 100.00
kmac_csr_aliasing 7.410s 0.000us 5 5 100.00
kmac_same_csr_outstanding 2.380s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.520s 0.000us 5 5 100.00
kmac_csr_rw 1.380s 0.000us 20 20 100.00
kmac_csr_aliasing 7.410s 0.000us 5 5 100.00
kmac_same_csr_outstanding 2.380s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.310s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.310s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.310s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.310s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.430s 0.000us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.350s 0.000us 20 20 100.00
kmac_sec_cm 114.660s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.350s 0.000us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 22.000s 0.000us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 85.860s 0.000us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 491.430s 0.000us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.310s 0.000us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 114.660s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 114.660s 0.000us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 114.660s 0.000us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 85.860s 0.000us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 22.000s 0.000us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 114.660s 0.000us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 367.730s 0.000us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 85.860s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 173.860s 0.000us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 90952696856236737649892846180287280225938105075375329139534967122489437116966 214
UVM_ERROR @ 18843257417 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 18843257417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_burst_write 62296173859225609427946181751131523880644897640582865591335644422231675793463 201
UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---