| V1 |
|
97.16% |
| V2 |
|
90.09% |
| V2S |
|
94.58% |
| V3 |
|
0.99% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| otp_ctrl_wake_up | 1.560s | 0.000us | 1 | 1 | 100.00 | |
| smoke | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 12.060s | 0.000us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 2.610s | 0.000us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| otp_ctrl_csr_rw | 2.370s | 0.000us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_bit_bash | 9.610s | 0.000us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_aliasing | 7.930s | 0.000us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 16 | 20 | 80.00 | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 7.620s | 0.000us | 16 | 20 | 80.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| otp_ctrl_csr_rw | 2.370s | 0.000us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 7.930s | 0.000us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| otp_ctrl_mem_walk | 2.300s | 0.000us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| otp_ctrl_mem_partial_access | 1.960s | 0.000us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dai_access_partition_walk | 1 | 1 | 100.00 | |||
| otp_ctrl_partition_walk | 14.590s | 0.000us | 1 | 1 | 100.00 | |
| init_fail | 279 | 300 | 93.00 | |||
| otp_ctrl_init_fail | 7.090s | 0.000us | 279 | 300 | 93.00 | |
| partition_check | 17 | 60 | 28.33 | |||
| otp_ctrl_background_chks | 22.080s | 0.000us | 3 | 10 | 30.00 | |
| otp_ctrl_check_fail | 15.770s | 0.000us | 14 | 50 | 28.00 | |
| regwen_during_otp_init | 50 | 50 | 100.00 | |||
| otp_ctrl_regwen | 12.380s | 0.000us | 50 | 50 | 100.00 | |
| partition_lock | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 115.680s | 0.000us | 50 | 50 | 100.00 | |
| interface_key_check | 50 | 50 | 100.00 | |||
| otp_ctrl_parallel_key_req | 45.920s | 0.000us | 50 | 50 | 100.00 | |
| lc_interactions | 250 | 250 | 100.00 | |||
| otp_ctrl_parallel_lc_req | 23.580s | 0.000us | 50 | 50 | 100.00 | |
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| otp_dai_errors | 47 | 50 | 94.00 | |||
| otp_ctrl_dai_errs | 37.790s | 0.000us | 47 | 50 | 94.00 | |
| otp_macro_errors | 18 | 50 | 36.00 | |||
| otp_ctrl_macro_errs | 29.300s | 0.000us | 18 | 50 | 36.00 | |
| test_access | 50 | 50 | 100.00 | |||
| otp_ctrl_test_access | 34.490s | 0.000us | 50 | 50 | 100.00 | |
| stress_all | 30 | 50 | 60.00 | |||
| otp_ctrl_stress_all | 273.060s | 0.000us | 30 | 50 | 60.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| otp_ctrl_intr_test | 2.340s | 0.000us | 50 | 50 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| otp_ctrl_alert_test | 3.320s | 0.000us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_errors | 8.100s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_errors | 8.100s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 2.610s | 0.000us | 5 | 5 | 100.00 | |
| otp_ctrl_csr_rw | 2.370s | 0.000us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 7.930s | 0.000us | 5 | 5 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 4.780s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 2.610s | 0.000us | 5 | 5 | 100.00 | |
| otp_ctrl_csr_rw | 2.370s | 0.000us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 7.930s | 0.000us | 5 | 5 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 4.780s | 0.000us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| tl_intg_err | 23 | 25 | 92.00 | |||
| otp_ctrl_tl_intg_err | 27.680s | 0.000us | 20 | 20 | 100.00 | |
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| prim_count_check | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| prim_fsm_check | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_intg_err | 27.680s | 0.000us | 20 | 20 | 100.00 | |
| sec_cm_secret_mem_scramble | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 12.060s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_digest | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 12.060s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_dai_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_kdi_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_lci_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_part_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_scrmbl_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_timer_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_dai_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_kdi_seed_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_kdi_entropy_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_lci_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_part_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_scrmbl_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_timer_integ_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_timer_cnsty_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_timer_lfsr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_dai_fsm_local_esc | 203 | 205 | 99.02 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_lci_fsm_local_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_kdi_fsm_local_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_part_fsm_local_esc | 218 | 250 | 87.20 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_macro_errs | 29.300s | 0.000us | 18 | 50 | 36.00 | |
| sec_cm_scrmbl_fsm_local_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_timer_fsm_local_esc | 203 | 205 | 99.02 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_dai_fsm_global_esc | 203 | 205 | 99.02 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_lci_fsm_global_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_kdi_fsm_global_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_part_fsm_global_esc | 218 | 250 | 87.20 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_macro_errs | 29.300s | 0.000us | 18 | 50 | 36.00 | |
| sec_cm_scrmbl_fsm_global_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| sec_cm_timer_fsm_global_esc | 203 | 205 | 99.02 | |||
| otp_ctrl_parallel_lc_esc | 31.570s | 0.000us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_part_data_reg_integrity | 279 | 300 | 93.00 | |||
| otp_ctrl_init_fail | 7.090s | 0.000us | 279 | 300 | 93.00 | |
| sec_cm_part_data_reg_bkgn_chk | 14 | 50 | 28.00 | |||
| otp_ctrl_check_fail | 15.770s | 0.000us | 14 | 50 | 28.00 | |
| sec_cm_part_mem_regren | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 115.680s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_sw_unreadable | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 115.680s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_sw_unwritable | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 115.680s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_lc_part_mem_sw_noaccess | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 115.680s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_access_ctrl_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 115.680s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 12.060s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 115.680s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_test_bus_lc_gated | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 12.060s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_test_tl_lc_gate_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 137.500s | 0.000us | 3 | 5 | 60.00 | |
| sec_cm_direct_access_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_regwen | 12.380s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_check_trigger_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 12.060s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_check_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 12.060s | 0.000us | 50 | 50 | 100.00 | |
| sec_cm_macro_mem_integrity | 18 | 50 | 36.00 | |||
| otp_ctrl_macro_errs | 29.300s | 0.000us | 18 | 50 | 36.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| otp_ctrl_low_freq_read | 1 | 1 | 100.00 | |||
| otp_ctrl_low_freq_read | 16.180s | 0.000us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 100 | 0.00 | |||
| otp_ctrl_stress_all_with_rand_reset | 26.580s | 0.000us | 0 | 100 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | ||||
| otp_ctrl_csr_mem_rw_with_rand_reset | 53103091838525295039791685465566653723330061091718234884118550678356723738905 | 92 |
UVM_ERROR @ 107664645 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 107664645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 100652559277285332587062018490262647241547536444550575306409320058397075028181 | 92 |
UVM_ERROR @ 45171512 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 45171512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 75630715715884240024830916552468503592793696007470851516494364030684653246314 | 92 |
UVM_ERROR @ 51545564 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 51545564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 41938667397942602801312557362160441133115200116742280025190245717462700064636 | 98 |
UVM_ERROR @ 892740979 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 892740979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 110587655775885340034877880977876988777373027364871894449015154489136869933947 | 99 |
UVM_ERROR @ 27924400 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27924400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 74086840151520237757187006730070024222395042728841491995510193462585540451873 | 92 |
UVM_ERROR @ 28609004 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28609004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 83019415405184424834477017703987174742211600278360835970206140400739523438072 | 93 |
UVM_ERROR @ 428787728 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 428787728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 62292279799103481701620707340706619577721020704724410255285330852627333771343 | 93 |
UVM_ERROR @ 431168172 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 431168172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 77411203495946986405295372450736344046637622104334950673619317072242687884902 | 101 |
UVM_ERROR @ 27720260 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27720260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 103466232971288049418301252078085318066779245972791949871065746345090254329098 | 95 |
UVM_ERROR @ 430727941 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 430727941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 13292946589331201069158992159870668600772611530799068190053700178588113125295 | 232 |
UVM_ERROR @ 2487683609 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 2487683609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 105197412893058130262254755436412485042760053368617399953856628567436874373701 | 97 |
UVM_ERROR @ 113671996 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 113671996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 40936172405371776287409878599470757502473987645219641053802939970721468115137 | 105 |
UVM_ERROR @ 107799667 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 107799667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 76182104253353664443298847259994408990335516632096995931154992337594845455803 | 92 |
UVM_ERROR @ 434503962 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 434503962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 66817203584594374262312695780003770051788788073514709953021892043943373384961 | 92 |
UVM_ERROR @ 433736257 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 433736257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 12069059025206267303182989181247146235124352874980782453999022392013892548350 | 187 |
UVM_ERROR @ 61065507 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 61065507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 25085737754696120027022101471268630659863580688960478140831518248291072325339 | 92 |
UVM_ERROR @ 112178943 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 112178943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 86758737856868617090754047126505554903180013670043295658720890120843407978889 | 101 |
UVM_ERROR @ 71833364 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 71833364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 35821929891312519441685290835359197459419655327160038173214687416615494994025 | 117 |
UVM_ERROR @ 467112320 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 467112320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 12488169701201010040084984954152251345420389463437745220994349030172896105085 | 95 |
UVM_ERROR @ 33115173 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 33115173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 57942328859398751259973111057430788605962195636008576433412932532078081335931 | 99 |
UVM_ERROR @ 28832457 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28832457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 77582223551525565967617736290750147345027306443231233695320236316509644520157 | 97 |
UVM_ERROR @ 444277396 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 444277396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 3983422474197520546021325496919304218897916381209319101539983133178212232139 | 93 |
UVM_ERROR @ 52771660 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 52771660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 49905696356681401412727499785014780832220582487767641115888300296948270468477 | 157 |
UVM_ERROR @ 62679074 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 62679074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 33702379048861723892307000494723476344215046064762134826950365253559862561697 | 99 |
UVM_ERROR @ 37618739 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 37618739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 53780417236398059958401813484434874739511923876703895393640209743819688058361 | 92 |
UVM_ERROR @ 120897739 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 120897739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 36408084063624813613807870718751370508122041794640133646115914392807407138865 | 92 |
UVM_ERROR @ 80529656 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 80529656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 54800435391796462062862418629483987021000526657252119288002496966302407514255 | 6111 |
UVM_ERROR @ 10254807096 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 10254807096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 42039606867093409047335931282243901086573058653599739607462297663805878196533 | 92 |
UVM_ERROR @ 429087913 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 429087913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 12526027260940727609992296761215345059212589617132302386831908834056869895868 | 190 |
UVM_ERROR @ 14129930594 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 14129930594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 70356510734400172141918951369035316108355921068280819412005134388044120980691 | 95 |
UVM_ERROR @ 431092407 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 431092407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 110137970470789241494182803461090330686399940983666093621715061000583564716015 | 93 |
UVM_ERROR @ 53578088 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53578088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 80317289902857859946597467891649814766612575846817727428746900930008959825263 | 97 |
UVM_ERROR @ 35276028 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 35276028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 22581140132926174430840351817384390116014585958689516485307070274295021478489 | 92 |
UVM_ERROR @ 435189199 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 435189199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 25660319211029578264725089089329077000348024000470144919483728556997655234321 | 22050 |
UVM_ERROR @ 640734406 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 640734406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 57147952226471900179893084085905846626644704918616735224532468949106434909849 | 94 |
UVM_ERROR @ 55213716 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 55213716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 15805674158053475005729247688527100743080810046678413483277216101955751085843 | 92 |
UVM_ERROR @ 89734936 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 89734936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 32763333393469027236919030098828440657760676033355583033634335461377863142233 | 95 |
UVM_ERROR @ 429857031 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 429857031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 34218990956879356584114167368475579501090132843376733166549693066276254993140 | 92 |
UVM_ERROR @ 429086621 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 429086621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 70955525137129288682594964317532515788353454216401502083806615606411373910397 | 93 |
UVM_ERROR @ 36182171 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 36182171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 41401938701834362487022295384830712183627630007738669831115139880077643078608 | 92 |
UVM_ERROR @ 55089198 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 55089198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 28253477929145297224373845009859109563340808356303020448491715729928967992057 | 95 |
UVM_ERROR @ 51609153 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 51609153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 17515561171597213163747275968869445811616542517896011538220949878839199583787 | 92 |
UVM_ERROR @ 50800076 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 50800076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 31366986601437819429319567483783900278899208511433711933692757235989108544689 | 95 |
UVM_ERROR @ 104167640 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 104167640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 61592785444644241903457233423591226879240989919971558564850157922647965668767 | 92 |
UVM_ERROR @ 429660114 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 429660114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 56660581155710704577304196297944444963054966173219021513170244370909648291201 | 100 |
UVM_ERROR @ 111735626 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 111735626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 71274193403800438366610035841239735148027174963722275776339497684286048405150 | 95 |
UVM_ERROR @ 52934553 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 52934553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 68993653297832049081677665004065830408595727125179555262555316831784818085198 | 330 |
UVM_ERROR @ 166872678 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 166872678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 69957260904871457392529005584598550531560465338660387188156079420614584616374 | 92 |
UVM_ERROR @ 108085555 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 108085555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 67866879373832230854326473427907331135214566947614464623398755614795642828100 | 92 |
UVM_ERROR @ 56911128 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 56911128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 42924327691668280651525971061098001772416210368085778553457584166552566938270 | 99 |
UVM_ERROR @ 53441493 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53441493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 28545816979825474701158306429421674936446480925480363077822890046339517159572 | 95 |
UVM_ERROR @ 27821793 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27821793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 59766804097915803566382631648293908365549447547600894617828620369026290207995 | 95 |
UVM_ERROR @ 29128064 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 29128064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 11826068967410126148546120906275463066197676394881815350887676574203200185254 | 298 |
UVM_ERROR @ 127319820 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 127319820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 62179463773635327614973036264723763385902800599462514830706234184712278126513 | 103 |
UVM_ERROR @ 27011199 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27011199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 75783446419835611103448322849269756068812745342613984449073451726267053041963 | 101 |
UVM_ERROR @ 36803779 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 36803779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 18542096861796391659323074224113352183724552058449969647509770105837106357697 | 93 |
UVM_ERROR @ 53120602 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53120602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 10721440174380077873355323793597780066234014772891224449902559458359327242365 | 93 |
UVM_ERROR @ 107580751 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 107580751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 85061413202306622812730033457321861235179145917467710848260554982227827650604 | 99 |
UVM_ERROR @ 445905952 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 445905952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 107273313506045921707464629130748138171850216488308833975770996814736707590417 | 102 |
UVM_ERROR @ 434828348 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 434828348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 84186229777112250290614029400698928298858895880650807444388551245429503873475 | 92 |
UVM_ERROR @ 55723087 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 55723087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 106505813472563979661558938401210811764106956736559036357650158119779369010229 | 92 |
UVM_ERROR @ 66749239 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 66749239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 56479639665021661139306886803241635248724234780692168114172349105987062693709 | 92 |
UVM_ERROR @ 31957875 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 31957875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 100251855054680630073935949918270559700782650412618966917241264260937823633547 | 92 |
UVM_ERROR @ 27565636 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27565636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 59946229700549259558135574465940416043754515205731085542795220095697778933621 | 92 |
UVM_ERROR @ 116904553 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 116904553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 47274156254224046108864265848767064233558497962318802714204480451765722252005 | 97 |
UVM_ERROR @ 103434350 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 103434350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 87883294445185259896258163785496112682626308769188634911279917899216576454363 | 95 |
UVM_ERROR @ 54157350 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 54157350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 21560568935576849771413819136999004212497314641151480201948428570818515428654 | 115 |
UVM_ERROR @ 114214285 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 114214285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 30949225164540780787621829196085739304870590836868284827493578843121849235270 | 101 |
UVM_ERROR @ 104781367 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 104781367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 33867453956021940617332776500350345024858059488042032762559264068184361333432 | 95 |
UVM_ERROR @ 26285688 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26285688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 25718513524465783440904941054878407930552712668213388217056558326554701533935 | 94 |
UVM_ERROR @ 34675183 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 34675183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 67678877194494873411088228121017295042314729641247288262191867867902860044529 | 92 |
UVM_ERROR @ 48444885 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 48444885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 96869631091922234122057799493825658454852434160582863964265750419799485450287 | 95 |
UVM_ERROR @ 40128088 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 40128088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 11419973953631859860892480239837262924366246963129789501383573105302863756163 | 99 |
UVM_ERROR @ 52415484 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 52415484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 1729525905547116732959981080590942509595811938774114591887630349574084548605 | 183 |
UVM_ERROR @ 283674786 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 283674786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 949291417360741808273549876761391657181586390889912378918722970957989460069 | 224 |
UVM_ERROR @ 485927004 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 485927004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 96283038952227351240758847545471060355314657175659736787658468368098822825872 | 95 |
UVM_ERROR @ 108640599 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 108640599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 114037470069605315520604226086728905263819795174488667798496865015685693531747 | 95 |
UVM_ERROR @ 26108446 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26108446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 31534495327590206334556321935695530001080297275671658434330778740099278886311 | 98 |
UVM_ERROR @ 26241680 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26241680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 75642290429133398278267377675811777264104745983511697454955841180384005944104 | 190 |
UVM_ERROR @ 2461439537 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 2461439537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 110671562611346509431149771365399521790998561140511778390437612188447908297667 | 103 |
UVM_ERROR @ 74367014 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 74367014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 60637415277207057937337921709559076003745186215339806670737751374491512295275 | 93 |
UVM_ERROR @ 58988856 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 58988856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 87894932630183847647788605909858794313553319601778856372769876703139908169503 | 95 |
UVM_ERROR @ 52878049 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 52878049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 67489214378614134070668771519503746205605795352025953151648340107830988444439 | 101 |
UVM_ERROR @ 118984242 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 118984242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 49457446204226372438100681829252480431511282761597088174486665838463146418763 | 95 |
UVM_ERROR @ 429968575 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 429968575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 100794540067632773586788063022926458192523812712613281533552616240976668959572 | 100 |
UVM_ERROR @ 37890084 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 37890084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 109601472520352691222502607902762519650559333810779455372229704571095617831361 | 92 |
UVM_ERROR @ 30021152 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 30021152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 94935284770786824184625653743481291064286018511609203043890966645365650456920 | 95 |
UVM_ERROR @ 56842047 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 56842047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 103434499839196472137590852587596480029005611419691846654110667317444404243463 | 93 |
UVM_ERROR @ 26104897 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26104897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 104205962630100602410432110493348025310181782265549694090158757650021347939372 | 92 |
UVM_ERROR @ 36201584 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 36201584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 110489619816007886016171694490288715138770416165413354323384285443339038628869 | 669 |
UVM_ERROR @ 716135027 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 716135027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 3412315202884229530409120788906939527044270098925328231829653720113551799264 | 92 |
UVM_ERROR @ 41245426 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 41245426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 91106543180756811030302001210811550789443584815306155609922182665284212791620 | 92 |
UVM_ERROR @ 32657961 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 32657961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 103973361711611084706777856657636746688120338564217723630123994874622457436742 | 12913 |
UVM_ERROR @ 1215926030 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 1215926030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 104001524715857990219402412501987806021200322352978115942485750456255631001479 | 95 |
UVM_ERROR @ 63504177 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 63504177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 99744177958714718464208711640451739984964545816205898692094571813984488835876 | 92 |
UVM_ERROR @ 65190194 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 65190194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 15667547058022422734855404335844763840343759845300450188950886544402748667705 | 93 |
UVM_ERROR @ 29400899 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 29400899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 73972904833758388640138332413726048052168789172956981971924400273704773764883 | 92 |
UVM_ERROR @ 43144015 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 43144015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 493369331963657408738346780934739856402247454117634982402881631223866808009 | 93 |
UVM_ERROR @ 26174250 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26174250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 46647187162953917965522015173257466574245874415730845865959415186229274629067 | 92 |
UVM_ERROR @ 454483624 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 454483624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 13815597165185055039738120465549521039098259074311168361648522480472665555213 | 95 |
UVM_ERROR @ 55331632 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 55331632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 12974440481106882451037546485286436779659618941155543793329091349949705515082 | 93 |
UVM_ERROR @ 432147128 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 432147128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 30252399954766452453823011455281877492290894855242948465442189059097585707703 | 95 |
UVM_ERROR @ 26000495 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26000495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! | ||||
| otp_ctrl_background_chks | 47124799368674731214247006597809535078216372306169810131623623228220508278058 | 7066 |
UVM_ERROR @ 2754698972 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 2754698972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 19654727286013799842304902775703022201058668072453864727740691936086414685608 | 9266 |
UVM_ERROR @ 12154939787 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 12154939787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 2117685649731776986941959122444278807837696847644231078938141252670606252911 | 26407 |
UVM_ERROR @ 5289980670 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 5289980670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 45618383195338335394195034382601739625394425064836938821740905451523092126594 | 5198 |
UVM_ERROR @ 430001289 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 430001289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 2657722706427912873128787635974997197284852570474890563236489299388166533360 | 2986 |
UVM_ERROR @ 1142334633 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1142334633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 69608037794562187578583691249182736786054574802809393784706588001751899331339 | 3111 |
UVM_ERROR @ 1675707251 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1675707251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 48952324463548834808574696803340635670734644091115961898367387708733788729718 | 3787 |
UVM_ERROR @ 7365973249 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 7365973249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 113744690215703749186325510476701238198120424184713442389726987201080429518134 | 50262 |
UVM_ERROR @ 3097810589 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 3097810589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 41247517061588130923558090371205380547441003771438605689197591858536746824589 | 6276 |
UVM_ERROR @ 587616409 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 587616409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 71913230463109210562628221890454543120099481723791107814837861420913143188008 | 12597 |
UVM_ERROR @ 17550219518 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 17550219518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 2084270834278231818866355598232660829133689292690936640362433454954496379032 | 12027 |
UVM_ERROR @ 3147171409 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 3147171409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 42035228919584695228175068173675658067897118621080588578846242374835504190851 | 30938 |
UVM_ERROR @ 2703209565 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 2703209565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 18821944479916643614113542186357777706880602405314002005900997037215170298169 | 39861 |
UVM_ERROR @ 11514183724 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 11514183724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 70793302758298643185635422044514723726435064399989849535383889783753146705896 | 51595 |
UVM_ERROR @ 28531742379 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 28531742379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 97129082379575500845991285315556414615449910849781081429972304562283004450968 | 70387 |
UVM_ERROR @ 32437995051 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 32437995051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 100632516705149526791757684029039125717148512784879365874057354916720131139403 | 110077 |
UVM_ERROR @ 129381834537 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 129381834537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 28743462904064242287656632959411041717555882153715186530677001004673903786759 | 74917 |
UVM_ERROR @ 12775685119 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 12775685119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 108268326187928426586388143747695295066526305354320995404910995441730743660696 | 5098 |
UVM_ERROR @ 346542895 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 346542895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 22735075400418037191542559188132908219038649780771781222181005386597102946879 | 42972 |
UVM_ERROR @ 18070349368 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 18070349368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 88500157642695067907288258123208551875932556360469294647731544867133145340685 | 59071 |
UVM_ERROR @ 29213387695 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 29213387695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 52821499707381946541029024955195519780726910872022278335049609755054471003624 | 6932 |
UVM_ERROR @ 15454825341 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 15454825341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 56017426676551194277071164269742301325060252941241605682576499057028039671183 | 53031 |
UVM_ERROR @ 18023960419 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 18023960419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* | ||||
| otp_ctrl_dai_errs | 50742348964643118839084342396795764367770390875514007763288321147100768899220 | 1953 |
UVM_ERROR @ 1116594176 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3003624739 [0xb307ad23] vs 3149922155 [0xbbbfff6b]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1116594176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 37969344722574954665246419733278367214227278271517543310092054775519483042347 | 325 |
UVM_ERROR @ 119701469 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 119701469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 34600980830905849766082889164361448382747395356979445013615854881213911609197 | 3064 |
UVM_ERROR @ 151455278 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 12288 [0x3000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 151455278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 51518652746885935337049868424706752325975185524246387204488194151317800107208 | 6556 |
UVM_ERROR @ 7579462749 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1790606058 [0x6aba7aea] vs 1807645678 [0x6bbe7bee]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 7579462749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 56385103044345466790665292905014552435133657245334122112729184109298917790760 | 687 |
UVM_ERROR @ 229489521 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2712648381 [0xa1afbabd] vs 2712646333 [0xa1afb2bd]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 229489521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 44642629953565220716073278594276645227837914505592889834752680170609071753630 | 6268 |
UVM_ERROR @ 4433387429 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3568562139 [0xd4b3efdb] vs 3568529371 [0xd4b36fdb]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 4433387429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 65295564427244927087709397155283686384540577475559365954232194952907007923268 | 2248 |
UVM_ERROR @ 668752935 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 668752935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 42449323069635101159668164572242371571496957505331037890218693132584427635373 | 57459 |
UVM_ERROR @ 1585387813 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1983640409 [0x763bf359]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1585387813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 113988021663774954318417022044437356014052445880456470235126274918013834489326 | 6733 |
UVM_ERROR @ 776292355 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 776292355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 99397841636250028768249676830561913558899420619368476922504299971793972732472 | 862 |
UVM_ERROR @ 1991113763 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1991113763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 26285408075708117207623903591649180359548957413246260721109520839385488516980 | 471 |
UVM_ERROR @ 68736963 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 130 [0x82]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 68736963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 29382344822640222480162899059660213622073964326046983865542955837188890006450 | 6110 |
UVM_ERROR @ 1663656698 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8192 [0x2000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1663656698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 89940221877069374138720938095814016528696284456002134721523581953738085224039 | 926 |
UVM_ERROR @ 2069045400 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (377844533 [0x16857335] vs 377844517 [0x16857325]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2069045400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 23637901653888586303001352043775001397145586523770744148419430547684599008107 | 21167 |
UVM_ERROR @ 634626200 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 36864 [0x9000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 634626200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 80310557723011559252610681811271447425737246598656971581674806031924543256201 | 48377 |
UVM_ERROR @ 11197409617 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1125125749 [0x43100e75] vs 3474054911 [0xcf11deff]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 11197409617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 106135103742317189099487844339233702673176459227396102834431253584873033224006 | 4696 |
UVM_ERROR @ 942823082 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2048 [0x800]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 942823082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 3580610511461637523267702355900262858974942829469746500862645847013626486962 | 1436 |
UVM_ERROR @ 2513486800 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (293926968 [0x1184f838] vs 293926960 [0x1184f830]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2513486800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 2081540784824672005056738579302309439160267263999271644685886744273462730725 | 2889 |
UVM_ERROR @ 2324317570 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16640 [0x4100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2324317570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 59630608081351817497611871960987388218769722794284260293171912858934028580972 | 3694 |
UVM_ERROR @ 564712930 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 564712930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 86090573126028854618991968014673646527787449019979217995311589746506152833808 | 12199 |
UVM_ERROR @ 5736965037 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 5736965037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 93945030747169250311090015067897219471941194486542637884603689430128802970559 | 883 |
UVM_ERROR @ 81818574 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4222802802 [0xfbb2db72] vs 4222810992 [0xfbb2fb70]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 81818574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 52217201959402852421774726647592202429721737524555431811685850829986680974307 | 1779 |
UVM_ERROR @ 314883662 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1055560232 [0x3eea9228] vs 1055560233 [0x3eea9229]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 314883662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 20533903082300347293282712973497875645694121851631270583201602690832096183268 | 20636 |
UVM_ERROR @ 1529953545 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4260797104 [0xfdf69ab0] vs 4260796592 [0xfdf698b0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1529953545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 27934056197624679005913085542692211889670733677018964833154835522348449382349 | 11703 |
UVM_ERROR @ 1762305532 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2216002207 [0x8415829f] vs 2216002079 [0x8415821f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1762305532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 49116539407055269864864923668492434060896172464579620083433881153498048132312 | 1056 |
UVM_ERROR @ 698573905 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2048 [0x800]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 698573905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 101236478942916001409339700742693185735515261061903363253400301550108296780291 | 1759 |
UVM_ERROR @ 71507986 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2048 [0x800]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 71507986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 34472018777474906032317736791778912664134250495427107994705743907309510822456 | 1147 |
UVM_ERROR @ 774160511 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2584007527 [0x9a04d367] vs 2584005479 [0x9a04cb67]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 774160511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 35756489887112413690513314882350562031741552513860538215292898664115287872985 | 6684 |
UVM_ERROR @ 12099571276 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4257490653 [0xfdc426dd] vs 4260163325 [0xfdeceefd]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 12099571276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 17285221665963030237445528233636491904758587438534977660241681867871908655218 | 2465 |
UVM_ERROR @ 1076338799 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1076338799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 65088527796605872612862716425283590808781772354073109817172524488957242238702 | 407 |
UVM_ERROR @ 130259279 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 130259279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_dai_errs | 7243921295484696543558969469339708258370888089740460655469609083002836141432 | 5097 |
UVM_ERROR @ 3691161341 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (281494705 [0x10c744b1] vs 902259959 [0x35c764f7]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3691161341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 57920783579808859350844869916882195662798949527389060130676895177962942723422 | 12675 |
UVM_ERROR @ 2128474848 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2128474848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 8993503099698389310594658268394494552599846609517790443375326022925436827583 | 15032 |
UVM_ERROR @ 1339259618 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16 [0x10]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1339259618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 21748125114599245717970024699243109541648602329016242648206178006042816719135 | 14002 |
UVM_ERROR @ 6427096249 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (45009415 [0x2aeca07] vs 45009431 [0x2aeca17]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 6427096249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 92470047855881711910666236156748854625464047020308002360675846667783673055121 | 381 |
UVM_ERROR @ 102890582 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 102890582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 41914842273595064981281827323823369202813678061752675397083347352054801535414 | 1512 |
UVM_ERROR @ 1367791801 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3383047570 [0xc9a53592] vs 3383047634 [0xc9a535d2]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1367791801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 40831500049300756799762050740172362170489968730761949931047395570153087665983 | 11913 |
UVM_ERROR @ 6543855667 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4127512917 [0xf604d955] vs 4127510869 [0xf604d155]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 6543855667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 79820406295574430558059462140828199373091509605006531779267858105587123087879 | 269 |
UVM_ERROR @ 1674544370 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2041440409 [0x79ade899] vs 2041424009 [0x79ada889]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1674544370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 25443537869764766601971745065946286772101572071626940345071101696071110644134 | 7796 |
UVM_ERROR @ 542329985 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (991353505 [0x3b16daa1] vs 991361697 [0x3b16faa1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 542329985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 108146099989058114652628089632847256472497128154627076606614754019089173627219 | 4184 |
UVM_ERROR @ 272264681 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 272264681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 9619642527809228170814472807513878796352708593171078591892949020731847528171 | 15157 |
UVM_ERROR @ 1030825041 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2539663666 [0x97603132] vs 4286444858 [0xff7df53a]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1030825041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 14311326476258228323603783877680357807522450060431488905956778904986350950521 | 1174 |
UVM_ERROR @ 409267097 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1024 [0x400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 409267097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 73010204665250859662687400022149580921232241282545803064146788128189516019198 | 2225 |
UVM_ERROR @ 1079728741 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1079728741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 16353328989658976376665168315541957315031631222704183090789876998321794454992 | 1825 |
UVM_ERROR @ 239947777 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1024 [0x400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 239947777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 48353659189824237823826161984446379259026066207473158239480489888488902396242 | 2797 |
UVM_ERROR @ 135242335 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 135242335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 52634554880879949383967757363631900215849360930506326198384133326451057122066 | 7983 |
UVM_ERROR @ 1241865215 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1596873074 [0x5f2e5972] vs 1596873058 [0x5f2e5962]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1241865215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 92173207330866375093028762196729789109224512475011494769704658124187197284206 | 2670 |
UVM_ERROR @ 469696502 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 469696502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 108065164833796374843898380010623295015951918889124923639163347605140149544388 | 349 |
UVM_ERROR @ 83421784 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2048 [0x800]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 83421784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 89779167887775441700301347642037065819309026050542948003441972524099767451596 | 2115 |
UVM_ERROR @ 163153458 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 163153458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 62423265621175523709474254887429627103693452628454522952313107605373398005345 | 5276 |
UVM_ERROR @ 290806088 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2179192788 [0x81e3d7d4] vs 2179192276 [0x81e3d5d4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 290806088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 65383292648100251471205307736758471967517272670250556631018995477152066547400 | 5025 |
UVM_ERROR @ 4905428589 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 4905428589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 97909383298861798655117677332100075559059225628393618160819002338702657793865 | 261 |
UVM_ERROR @ 145848645 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1442544440 [0x55fb7b38] vs 1442544568 [0x55fb7bb8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 145848645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 59569350674732641978268158816395886783692896998417955513561430624185422689130 | 5854 |
UVM_ERROR @ 1167135866 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1167135866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 73733463191500305141184725801534678698029172484833595044389210047924669232922 | 2763 |
UVM_ERROR @ 387397830 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8256 [0x2040]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 387397830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 100626243024899139287679868565960516174896697434640115027060499213984763041620 | 6618 |
UVM_ERROR @ 12759855928 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 33792 [0x8400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 12759855928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 90710436226718869750887153937667966949454670979470984145066952124418231870303 | 1505 |
UVM_ERROR @ 556208808 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1024 [0x400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 556208808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 20447778989349121989635736331890699971925374367335236680390224098574360627164 | 10569 |
UVM_ERROR @ 427436733 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2218325919 [0x8438f79f] vs 2218308511 [0x8438b39f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 427436733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 77084833252186452870238928277887801694701727676200547051559958226780706723833 | 3188 |
UVM_ERROR @ 213731115 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 213731115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:* | ||||
| otp_ctrl_macro_errs | 2391234518291606235305716019823537526454661970448762125818521921020881357903 | 901 |
UVM_ERROR @ 77435477 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 77435477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 89511729899802206263250915816663180426971385085993394486916034014916192525314 | 1091 |
UVM_ERROR @ 786960027 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 786960027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 38972392370910033896034768684461443429483925174772459912363307091058104641338 | 2524 |
UVM_ERROR @ 265137964 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 265137964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 75723420796768151409458037994603732080360537589180402743426092043880845067952 | 8438 |
UVM_ERROR @ 1467463972 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 1467463972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_dai_errs | 70490335577004599750860963096527959723308098057756182349680913945229394806778 | 937 |
UVM_ERROR @ 128809375 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 128809375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 44372515491620236472015368414157406444094873102030983113125667901099076790369 | 5489 |
UVM_ERROR @ 903773128 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 903773128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 6452107320334269192917125970381524133873029901290038206218193176232424270696 | 729 |
UVM_ERROR @ 138854031 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 138854031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 26230955694614455883505132187413940331414495437930680102118649090614089819989 | 3581 |
UVM_ERROR @ 350236140 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 350236140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 23921138996244047219434283892399753365483936723715060166661567000499705560078 | 2424 |
UVM_ERROR @ 726550867 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 726550867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire | ||||
| otp_ctrl_sec_cm | 97150063379630764899122238045757710340049304571197813526955084384810501727128 | 287 |
UVM_ERROR @ 12105962615 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 12105962615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_sec_cm | 80799119097437191314457862230936801465339275162723754123598538329276722275267 | 121 |
UVM_ERROR @ 494223100 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 494223100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:691) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr | ||||
| otp_ctrl_check_fail | 69165272281558941970122555514030527201969379044682935426090573968613753824881 | 2082 |
UVM_ERROR @ 378083147 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 378083147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 34211746814591727832805892273134638452354775323186418025096540008925404404250 | 163 |
UVM_ERROR @ 56950785 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 56950785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 21902720037979179588788323925921572322359612892879212258823894846007156746966 | 2161 |
UVM_ERROR @ 1077483960 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 1077483960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state | ||||
| otp_ctrl_check_fail | 79614237712713882471006169405514704347285936024380386593114952158308999263037 | 2255 |
UVM_ERROR @ 156139451 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 156139451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 80984252635194589696437189146579118279444416879804760745847167283809641195512 | 1517 |
UVM_ERROR @ 224972531 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 224972531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 97032312029004906908144401562239078947151130231063278011247281404167446074071 | 18260 |
UVM_ERROR @ 9491487092 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 9491487092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 73979582076881883024990177728727189200450105506620568801067669898568928344776 | 2856 |
UVM_ERROR @ 993585492 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 993585492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 66620159175450115129829857528128110716142971792292520970279719583152444624685 | 4855 |
UVM_ERROR @ 1314986242 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1314986242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! | ||||
| otp_ctrl_init_fail | 10083275963862266932894511573247401799245353096358693706004325970567526766208 | 1077 |
UVM_ERROR @ 287071867 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 287071867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 38532657356821021689390680389230638527273389153331705330352905843541750393677 | 1787 |
UVM_ERROR @ 1285741655 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1285741655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 98194985511732552399849169071674184987237693275728795573778591235539452498562 | 1639 |
UVM_ERROR @ 2009701452 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 2009701452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 16247815212600857950721131897999071983086621640491345257013240823454328479350 | 1581 |
UVM_ERROR @ 272019218 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 272019218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 2116325571053163937530577446010919561015125304867638044653981497970739275841 | 1849 |
UVM_ERROR @ 255819868 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 255819868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 74799755610129933301413610432671109013503336421222984281672211298107151564820 | 3201 |
UVM_ERROR @ 90594917 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 90594917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 62346183766126862696842821926547872430717950738601211428839315793642589299731 | 2321 |
UVM_ERROR @ 179196951 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 179196951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 48976237519496886106980867794345645283591085021108134327596742661445610504706 | 1091 |
UVM_ERROR @ 377548810 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 377548810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 20480290512284903434070623794574457762025122011065572979520278185079053614925 | 2003 |
UVM_ERROR @ 123034727 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 123034727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 114563980555288242948300417324153709033804253522336389662782233874811917316290 | 1515 |
UVM_ERROR @ 379908101 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 379908101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 69055318131265188306738600585293492212395187983645378091114938129320119653510 | 2865 |
UVM_ERROR @ 325673487 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 325673487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 29848227909424524626399722945089690586963424212737903085774809390707434958347 | 2299 |
UVM_ERROR @ 2198318251 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 2198318251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 58209440258534968529561763794134733214186235860564206572536812448195682558837 | 1873 |
UVM_ERROR @ 415521674 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 415521674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 108139092120535665738902356618521427185518430623566752316288642244179564899652 | 1589 |
UVM_ERROR @ 232392991 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 232392991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 22546889742749198891442827110485086010134578687368855445058295441582776294909 | 2699 |
UVM_ERROR @ 1317396165 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1317396165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 97130078002463933765983683623863362658388346592982517444345921771746008840476 | 3833 |
UVM_ERROR @ 165883958 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 165883958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 4097843748249068043184901433115286611318306679107589190777488914444340929490 | 3631 |
UVM_ERROR @ 1263892366 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1263892366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 8481187448303020061864115894364704965975531042572527618378329896126108569355 | 2469 |
UVM_ERROR @ 1111231043 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1111231043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 8192005891166651584833734355899335681386556744244999587767342846711670054426 | 3979 |
UVM_ERROR @ 1597105437 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1597105437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 14740525152830858124965802477556293453116243250027772767265091525730374494963 | 2215 |
UVM_ERROR @ 1197221988 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1197221988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* | ||||
| otp_ctrl_check_fail | 94700302073354792175085205417945842535211399754144027078906466496187240430550 | 11898 |
UVM_ERROR @ 1335378618 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
UVM_INFO @ 1335378618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| otp_ctrl_check_fail | 16838784887039843975038385847547350364901043299654780834558143967190142104756 | 10134 |
UVM_ERROR @ 1441102567 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
UVM_INFO @ 1441102567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_macro_error does not trigger! | ||||
| otp_ctrl_init_fail | 48084917559287194742950246258633540897127458092824116216397535375676237404294 | 1343 |
UVM_ERROR @ 1816898916 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_macro_error does not trigger!
UVM_INFO @ 1816898916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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