Simulation Results: pwm

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.73 %
  • code
  • 96.50 %
  • assert
  • 98.00 %
  • func
  • 98.68 %
  • block
  • 99.42 %
  • line
  • 99.58 %
  • branch
  • 99.04 %
  • toggle
  • 90.87 %
Validation stages
V1
100.00%
V2
99.79%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwm_smoke 28.000s 0.000us 10 10 100.00
csr_hw_reset 5 5 100.00
pwm_csr_hw_reset 1.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
pwm_csr_rw 2.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
pwm_csr_bit_bash 7.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
pwm_csr_aliasing 2.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
pwm_csr_mem_rw_with_rand_reset 3.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
pwm_csr_rw 2.000s 0.000us 20 20 100.00
pwm_csr_aliasing 2.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dutycycle 25 25 100.00
pwm_rand_output 75.000s 0.000us 25 25 100.00
pulse 25 25 100.00
pwm_rand_output 75.000s 0.000us 25 25 100.00
blink 25 25 100.00
pwm_rand_output 75.000s 0.000us 25 25 100.00
heartbeat 25 25 100.00
pwm_rand_output 75.000s 0.000us 25 25 100.00
resolution 25 25 100.00
pwm_rand_output 75.000s 0.000us 25 25 100.00
multi_channel 25 25 100.00
pwm_rand_output 75.000s 0.000us 25 25 100.00
polarity 25 25 100.00
pwm_rand_output 75.000s 0.000us 25 25 100.00
phase 50 50 100.00
pwm_rand_output 75.000s 0.000us 25 25 100.00
pwm_phase 77.000s 0.000us 25 25 100.00
lowpower 25 25 100.00
pwm_rand_output 75.000s 0.000us 25 25 100.00
perf 10 10 100.00
pwm_perf 69.000s 0.000us 10 10 100.00
regwen 0 1 0.00
pwm_regwen 151.000s 0.000us 0 1 0.00
stress_all 25 25 100.00
pwm_stress_all 274.000s 0.000us 25 25 100.00
alert_test 50 50 100.00
pwm_alert_test 2.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
pwm_tl_errors 4.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
pwm_tl_errors 4.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
pwm_csr_hw_reset 1.000s 0.000us 5 5 100.00
pwm_csr_rw 2.000s 0.000us 20 20 100.00
pwm_csr_aliasing 2.000s 0.000us 5 5 100.00
pwm_same_csr_outstanding 2.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
pwm_csr_hw_reset 1.000s 0.000us 5 5 100.00
pwm_csr_rw 2.000s 0.000us 20 20 100.00
pwm_csr_aliasing 2.000s 0.000us 5 5 100.00
pwm_same_csr_outstanding 2.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
pwm_sec_cm 2.000s 0.000us 5 5 100.00
pwm_tl_intg_err 3.000s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
pwm_tl_intg_err 3.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
heartbeat_wrap 10 10 100.00
pwm_heartbeat_wrap 95.000s 0.000us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr pwm_reg_block.blink_param_* (addr=*)
pwm_regwen 17442246106430158927247969541669480855778190255969576484123898089889505128713 101
UVM_FATAL @ 23863640785 ps: (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr pwm_reg_block.blink_param_5 (addr=0xd7f18f58)
UVM_INFO @ 23863640785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---