Simulation Results: rstmgr

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.85 %
  • code
  • 99.66 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.31 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.480s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.070s 0.000us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.010s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 5.780s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 2.020s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.440s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.010s 0.000us 20 20 100.00
rstmgr_csr_aliasing 2.020s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.340s 0.000us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 2.390s 0.000us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.710s 0.000us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 5.730s 0.000us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 5.730s 0.000us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 5.730s 0.000us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 5.730s 0.000us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 40.930s 0.000us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.070s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 3.020s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 3.020s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.070s 0.000us 5 5 100.00
rstmgr_csr_rw 1.010s 0.000us 20 20 100.00
rstmgr_csr_aliasing 2.020s 0.000us 5 5 100.00
rstmgr_same_csr_outstanding 1.600s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.070s 0.000us 5 5 100.00
rstmgr_csr_rw 1.010s 0.000us 20 20 100.00
rstmgr_csr_aliasing 2.020s 0.000us 5 5 100.00
rstmgr_same_csr_outstanding 1.600s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 23.140s 0.000us 5 5 100.00
rstmgr_tl_intg_err 2.700s 0.000us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 23.140s 0.000us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 23.140s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 2.700s 0.000us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.320s 0.000us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 7.470s 0.000us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.480s 0.000us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 23.140s 0.000us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.010s 0.000us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.010s 0.000us 20 20 100.00