Simulation Results: spi_device/2p

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.09 %
  • code
  • 94.28 %
  • assert
  • 94.74 %
  • func
  • 99.26 %
  • line
  • 99.16 %
  • branch
  • 98.49 %
  • cond
  • 96.65 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
98.89%
V2S
100.00%
unmapped
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_device_flash_and_tpm 451.730s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.540s 0.000us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 2.590s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 25.820s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 18.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 4.400s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 2.590s 0.000us 20 20 100.00
spi_device_csr_aliasing 18.000s 0.000us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 1.030s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 2.540s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.190s 0.000us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.520s 0.000us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.790s 0.000us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 4.890s 0.000us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 4.890s 0.000us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 25.600s 0.000us 50 50 100.00
spi_device_tpm_sts_read 1.430s 0.000us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 42.000s 0.000us 50 50 100.00
pass_cmd_filtering 98 100 98.00
spi_device_pass_cmd_filtering 37.170s 0.000us 50 50 100.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
pass_addr_translation 98 100 98.00
spi_device_pass_addr_payload_swap 25.530s 0.000us 50 50 100.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
pass_payload_translation 98 100 98.00
spi_device_pass_addr_payload_swap 25.530s 0.000us 50 50 100.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
cmd_info_slots 48 50 96.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
cmd_read_status 98 100 98.00
spi_device_intercept 28.520s 0.000us 50 50 100.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
cmd_read_jedec 98 100 98.00
spi_device_intercept 28.520s 0.000us 50 50 100.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
cmd_read_sfdp 98 100 98.00
spi_device_intercept 28.520s 0.000us 50 50 100.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
cmd_fast_read 98 100 98.00
spi_device_intercept 28.520s 0.000us 50 50 100.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
cmd_read_pipeline 98 100 98.00
spi_device_intercept 28.520s 0.000us 50 50 100.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
flash_cmd_upload 50 50 100.00
spi_device_upload 32.560s 0.000us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 163.590s 0.000us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 163.590s 0.000us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 163.590s 0.000us 50 50 100.00
cmd_read_buffer 100 100 100.00
spi_device_flash_mode 35.170s 0.000us 50 50 100.00
spi_device_read_buffer_direct 24.450s 0.000us 50 50 100.00
cmd_dummy_cycle 98 100 98.00
spi_device_mailbox 163.590s 0.000us 50 50 100.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
quad_spi 48 50 96.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
dual_spi 48 50 96.00
spi_device_flash_all 356.460s 0.000us 48 50 96.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 27.080s 0.000us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 27.080s 0.000us 50 50 100.00
TPM_with_flash_or_passthrough_mode 50 50 100.00
spi_device_flash_and_tpm 451.730s 0.000us 50 50 100.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 331.320s 0.000us 50 50 100.00
stress_all 50 50 100.00
spi_device_stress_all 864.290s 0.000us 50 50 100.00
alert_test 50 50 100.00
spi_device_alert_test 1.150s 0.000us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.160s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 6.010s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 6.010s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.540s 0.000us 5 5 100.00
spi_device_csr_rw 2.590s 0.000us 20 20 100.00
spi_device_csr_aliasing 18.000s 0.000us 5 5 100.00
spi_device_same_csr_outstanding 4.060s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.540s 0.000us 5 5 100.00
spi_device_csr_rw 2.590s 0.000us 20 20 100.00
spi_device_csr_aliasing 18.000s 0.000us 5 5 100.00
spi_device_same_csr_outstanding 4.060s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_tl_intg_err 20.140s 0.000us 20 20 100.00
spi_device_sec_cm 1.620s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 20.140s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 49 50 98.00
spi_device_flash_mode_ignore_cmds 453.250s 0.000us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *
spi_device_flash_mode_ignore_cmds 50175083357912447095860260502085819138743370396996771007214081145879650370216 83
UVM_ERROR @ 40710757738 ps: (spi_device_pass_base_vseq.sv:705) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
UVM_INFO @ 43775849053 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/14
UVM_INFO @ 43775849053 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/14
tl_ul_fuzzy_flash_status_q[i] = 0xda2368
tl_ul_fuzzy_flash_status_q[i] = 0x93209c
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *
spi_device_flash_all 8107894739466547172643879635629511519374535716294525847936180274968207895425 82
UVM_ERROR @ 2504712971 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (12997632 [0xc65400] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xc65400 != exp 0x0
tl_ul_fuzzy_flash_status_q[i] = 0xfce5a0
UVM_INFO @ 3193194232 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/4
UVM_INFO @ 3193194232 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/4
tl_ul_fuzzy_flash_status_q[i] = 0xa07e18
spi_device_flash_all 22658762766585109055944837309722051697249446239223071487403708150293343451459 81
UVM_ERROR @ 8207437304 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (8422400 [0x808400] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x808400 != exp 0x0
UVM_INFO @ 8207437304 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/14
UVM_INFO @ 8207437304 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/14
UVM_INFO @ 12823057562 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/14
UVM_INFO @ 12823057562 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 3/14