Simulation Results: spi_host

 
05/04/2026 00:07:51 DVSim: v1.16.0 sha: 5ec693e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.81 %
  • code
  • 95.03 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.91%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 122.000s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 0.000us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 0.000us 20 20 100.00
spi_host_csr_aliasing 2.000s 0.000us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 2.000s 0.000us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 36.000s 0.000us 50 50 100.00
spi_host_error_cmd 2.000s 0.000us 50 50 100.00
spi_host_event 1188.000s 0.000us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 8.000s 0.000us 50 50 100.00
speed 50 50 100.00
spi_host_speed 8.000s 0.000us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 8.000s 0.000us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 30.000s 0.000us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 0.000us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 8.000s 0.000us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 8.000s 0.000us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 122.000s 0.000us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 122.000s 0.000us 50 50 100.00
stress_all 50 50 100.00
spi_host_stress_all 112.000s 0.000us 50 50 100.00
spien 50 50 100.00
spi_host_spien 182.000s 0.000us 50 50 100.00
stall 49 50 98.00
spi_host_status_stall 154.000s 0.000us 49 50 98.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 50.000s 0.000us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 36.000s 0.000us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 0.000us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 4.000s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 4.000s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 0.000us 5 5 100.00
spi_host_csr_rw 2.000s 0.000us 20 20 100.00
spi_host_csr_aliasing 2.000s 0.000us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 0.000us 5 5 100.00
spi_host_csr_rw 2.000s 0.000us 20 20 100.00
spi_host_csr_aliasing 2.000s 0.000us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 2.000s 0.000us 5 5 100.00
spi_host_tl_intg_err 2.000s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 2.000s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 742.000s 0.000us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_status_stall 24512192445776219449132467054693019146471075557761235080420803359279811569327 5704
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---