Simulation Results: adc_ctrl

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.08 %
  • code
  • 98.09 %
  • assert
  • 95.95 %
  • func
  • 19.21 %
  • line
  • 99.05 %
  • branch
  • 97.77 %
  • cond
  • 93.63 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.53%
V2S
96.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
adc_ctrl_smoke 21.460s 5961.712us 50 50 100.00
csr_hw_reset 5 5 100.00
adc_ctrl_csr_hw_reset 3.950s 1261.878us 5 5 100.00
csr_rw 20 20 100.00
adc_ctrl_csr_rw 2.520s 495.131us 20 20 100.00
csr_bit_bash 5 5 100.00
adc_ctrl_csr_bit_bash 265.500s 52234.857us 5 5 100.00
csr_aliasing 5 5 100.00
adc_ctrl_csr_aliasing 4.230s 835.704us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 3.220s 578.952us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
adc_ctrl_csr_rw 2.520s 495.131us 20 20 100.00
adc_ctrl_csr_aliasing 4.230s 835.704us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 50 50 100.00
adc_ctrl_filters_polled 1356.910s 489188.338us 50 50 100.00
filters_polled_fixed 50 50 100.00
adc_ctrl_filters_polled_fixed 1281.750s 487849.091us 50 50 100.00
filters_interrupt 50 50 100.00
adc_ctrl_filters_interrupt 1149.780s 506399.759us 50 50 100.00
filters_interrupt_fixed 50 50 100.00
adc_ctrl_filters_interrupt_fixed 1148.880s 488733.043us 50 50 100.00
filters_wakeup 50 50 100.00
adc_ctrl_filters_wakeup 1474.760s 601293.671us 50 50 100.00
filters_wakeup_fixed 50 50 100.00
adc_ctrl_filters_wakeup_fixed 1391.220s 575092.030us 50 50 100.00
filters_both 48 50 96.00
adc_ctrl_filters_both 1375.170s 600000.000us 48 50 96.00
clock_gating 35 50 70.00
adc_ctrl_clock_gating 1309.820s 534764.310us 35 50 70.00
poweron_counter 50 50 100.00
adc_ctrl_poweron_counter 16.160s 4900.027us 50 50 100.00
lowpower_counter 50 50 100.00
adc_ctrl_lowpower_counter 125.110s 42047.128us 50 50 100.00
fsm_reset 50 50 100.00
adc_ctrl_fsm_reset 369.780s 107252.765us 50 50 100.00
stress_all 48 50 96.00
adc_ctrl_stress_all 5942.970s 2641640.560us 48 50 96.00
alert_test 50 50 100.00
adc_ctrl_alert_test 2.480s 532.130us 50 50 100.00
intr_test 50 50 100.00
adc_ctrl_intr_test 2.720s 528.187us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
adc_ctrl_tl_errors 4.010s 406.374us 20 20 100.00
tl_d_illegal_access 20 20 100.00
adc_ctrl_tl_errors 4.010s 406.374us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
adc_ctrl_csr_hw_reset 3.950s 1261.878us 5 5 100.00
adc_ctrl_csr_rw 2.520s 495.131us 20 20 100.00
adc_ctrl_csr_aliasing 4.230s 835.704us 5 5 100.00
adc_ctrl_same_csr_outstanding 13.780s 3456.312us 20 20 100.00
tl_d_partial_access 50 50 100.00
adc_ctrl_csr_hw_reset 3.950s 1261.878us 5 5 100.00
adc_ctrl_csr_rw 2.520s 495.131us 20 20 100.00
adc_ctrl_csr_aliasing 4.230s 835.704us 5 5 100.00
adc_ctrl_same_csr_outstanding 13.780s 3456.312us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 24 25 96.00
adc_ctrl_sec_cm 6.620s 4291.778us 5 5 100.00
adc_ctrl_tl_intg_err 29.080s 7943.590us 19 20 95.00
sec_cm_bus_integrity 19 20 95.00
adc_ctrl_tl_intg_err 29.080s 7943.590us 19 20 95.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
adc_ctrl_stress_all_with_rand_reset 35.910s 373302.738us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_clock_gating 29650364302917084258758452910072127342774491279337082767532057934744963661093 342
UVM_INFO @ 210539463935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 113744315790049786182879538174567656223492264216992901592204454826049708518219 325
UVM_INFO @ 35617411740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 87009078236527174881766182429816184672767596184314950483861522730037206279601 342
UVM_INFO @ 194346750627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 21200439742656252080586482759536322840448872162150535027859659675889275318425 325
UVM_INFO @ 2016749782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 2732995783860263045567518514492234818068466211442538585187465755995903651107 336
UVM_INFO @ 2285457854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 42220872571795042639410603205217361812504357476792384308247636350948181135787 325
UVM_INFO @ 1673923287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 93364409819023769651306462985760833138004921642381379163869210809370138633882 342
UVM_INFO @ 226413135789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 107244761980545808786744957647900048753412994561774886279827557221602932541848 326
UVM_INFO @ 1731237294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 50888125186137206933923247812310011216189890549690601218414439684743523447102 359
UVM_INFO @ 342281369333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 78245545265012291694466324286942292704459537580047496631233757572521162857100 342
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 112268812949146772582978988342052677557067479447010306083781188727497007055079 357
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 36568185139249909975375552068427526476267503441595515035121504390717235544651 342
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 81677406987887971430646342278780074566488843995039973346149404368255330935472 342
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 55401864992942902634288875640999549241867050168839130474638995665696926191146 359
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 94004707450469528978796540083242537658001271502748243816779343017285141651310 342
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 65123347484620294747426007363094707835185883287481685559089079262298388603221 342
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 41826093625219060750757197053994468092859559634146233275433299641877530335261 342
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 47197042154151288629999448501149813991608578312228856746525667747829260549056 342
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 6743361072655190981847396871488722367050242449426252548333007709790530797651 357
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [adc_ctrl_common_vseq] expect alert:fatal_fault to fire
adc_ctrl_tl_intg_err 64686712347428746185507677106832635202603683225050356888808910189802688512619 351
UVM_INFO @ 1461643319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---