Simulation Results: aes/masked

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.26 %
  • code
  • 98.10 %
  • assert
  • 98.57 %
  • func
  • 95.11 %
  • block
  • 98.20 %
  • line
  • 99.38 %
  • branch
  • 94.98 %
  • toggle
  • 98.05 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.71%
V2S
97.47%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 173.141us 1 1 100.00
smoke 50 50 100.00
aes_smoke 7.000s 1478.143us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 3.000s 74.366us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 73.471us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 11.000s 135.617us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 19.000s 294.519us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 85.214us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 73.471us 20 20 100.00
aes_csr_aliasing 19.000s 294.519us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 7.000s 1478.143us 50 50 100.00
aes_config_error 89.000s 4865.005us 50 50 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
key_length 150 150 100.00
aes_smoke 7.000s 1478.143us 50 50 100.00
aes_config_error 89.000s 4865.005us 50 50 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
back2back 100 100 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
aes_b2b 48.000s 346.712us 50 50 100.00
backpressure 50 50 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 7.000s 1478.143us 50 50 100.00
aes_config_error 89.000s 4865.005us 50 50 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
aes_alert_reset 34.000s 159.814us 50 50 100.00
failure_test 150 150 100.00
aes_man_cfg_err 6.000s 275.295us 50 50 100.00
aes_config_error 89.000s 4865.005us 50 50 100.00
aes_alert_reset 34.000s 159.814us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 34.000s 105.278us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 12.000s 627.573us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 13.000s 393.681us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 34.000s 159.814us 50 50 100.00
stress 50 50 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
sideload 99 100 99.00
aes_stress 55.000s 3819.795us 50 50 100.00
aes_sideload 7.000s 95.262us 49 50 98.00
deinitialization 50 50 100.00
aes_deinit 6.000s 416.224us 50 50 100.00
stress_all 9 10 90.00
aes_stress_all 66.000s 1897.332us 9 10 90.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 10.000s 398.261us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 32.000s 83.653us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 5.000s 158.750us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 5.000s 158.750us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 3.000s 74.366us 5 5 100.00
aes_csr_rw 3.000s 73.471us 20 20 100.00
aes_csr_aliasing 19.000s 294.519us 5 5 100.00
aes_same_csr_outstanding 3.000s 146.700us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 3.000s 74.366us 5 5 100.00
aes_csr_rw 3.000s 73.471us 20 20 100.00
aes_csr_aliasing 19.000s 294.519us 5 5 100.00
aes_same_csr_outstanding 3.000s 146.700us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 49.000s 1532.405us 50 50 100.00
fault_inject 666 700 95.14
aes_fi 48.000s 2504.439us 49 50 98.00
aes_control_fi 59.000s 10003.581us 281 300 93.67
aes_cipher_fi 59.000s 10014.125us 336 350 96.00
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 4.000s 144.369us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 4.000s 144.369us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 4.000s 144.369us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 4.000s 144.369us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 978.868us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 9.000s 1172.513us 5 5 100.00
aes_tl_intg_err 5.000s 324.313us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 5.000s 324.313us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 34.000s 159.814us 50 50 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 4.000s 144.369us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 4.000s 144.369us 20 20 100.00
sec_cm_main_config_sparse 219 220 99.55
aes_smoke 7.000s 1478.143us 50 50 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
aes_alert_reset 34.000s 159.814us 50 50 100.00
aes_core_fi 25.000s 262.412us 69 70 98.57
sec_cm_gcm_config_sparse 269 270 99.63
aes_gcm_save_restore 10.000s 398.261us 100 100 100.00
aes_config_error 89.000s 4865.005us 50 50 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
aes_core_fi 25.000s 262.412us 69 70 98.57
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 4.000s 144.369us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 4.000s 56.286us 50 50 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
sec_cm_key_sideload 99 100 99.00
aes_stress 55.000s 3819.795us 50 50 100.00
aes_sideload 7.000s 95.262us 49 50 98.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 4.000s 56.286us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 4.000s 56.286us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 4.000s 56.286us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 4.000s 56.286us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 4.000s 56.286us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 55.000s 3819.795us 50 50 100.00
sec_cm_main_fsm_sparse 49 50 98.00
aes_fi 48.000s 2504.439us 49 50 98.00
sec_cm_main_fsm_redun 716 750 95.47
aes_fi 48.000s 2504.439us 49 50 98.00
aes_control_fi 59.000s 10003.581us 281 300 93.67
aes_cipher_fi 59.000s 10014.125us 336 350 96.00
aes_ctr_fi 36.000s 175.593us 50 50 100.00
sec_cm_cipher_fsm_sparse 49 50 98.00
aes_fi 48.000s 2504.439us 49 50 98.00
sec_cm_cipher_fsm_redun 666 700 95.14
aes_fi 48.000s 2504.439us 49 50 98.00
aes_control_fi 59.000s 10003.581us 281 300 93.67
aes_cipher_fi 59.000s 10014.125us 336 350 96.00
sec_cm_cipher_ctr_redun 336 350 96.00
aes_cipher_fi 59.000s 10014.125us 336 350 96.00
sec_cm_ctr_fsm_sparse 49 50 98.00
aes_fi 48.000s 2504.439us 49 50 98.00
sec_cm_ctr_fsm_redun 380 400 95.00
aes_fi 48.000s 2504.439us 49 50 98.00
aes_control_fi 59.000s 10003.581us 281 300 93.67
aes_ctr_fi 36.000s 175.593us 50 50 100.00
sec_cm_ghash_fsm_sparse 49 50 98.00
aes_fi 48.000s 2504.439us 49 50 98.00
sec_cm_ctrl_sparse 716 750 95.47
aes_fi 48.000s 2504.439us 49 50 98.00
aes_control_fi 59.000s 10003.581us 281 300 93.67
aes_cipher_fi 59.000s 10014.125us 336 350 96.00
aes_ctr_fi 36.000s 175.593us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 34.000s 159.814us 50 50 100.00
sec_cm_main_fsm_local_esc 716 750 95.47
aes_fi 48.000s 2504.439us 49 50 98.00
aes_control_fi 59.000s 10003.581us 281 300 93.67
aes_cipher_fi 59.000s 10014.125us 336 350 96.00
aes_ctr_fi 36.000s 175.593us 50 50 100.00
sec_cm_cipher_fsm_local_esc 716 750 95.47
aes_fi 48.000s 2504.439us 49 50 98.00
aes_control_fi 59.000s 10003.581us 281 300 93.67
aes_cipher_fi 59.000s 10014.125us 336 350 96.00
aes_ctr_fi 36.000s 175.593us 50 50 100.00
sec_cm_ctr_fsm_local_esc 380 400 95.00
aes_fi 48.000s 2504.439us 49 50 98.00
aes_control_fi 59.000s 10003.581us 281 300 93.67
aes_ctr_fi 36.000s 175.593us 50 50 100.00
sec_cm_ghash_fsm_local_esc 139 140 99.29
aes_fi 48.000s 2504.439us 49 50 98.00
aes_ghash_fi 9.000s 70.736us 90 90 100.00
sec_cm_data_reg_local_esc 666 700 95.14
aes_fi 48.000s 2504.439us 49 50 98.00
aes_control_fi 59.000s 10003.581us 281 300 93.67
aes_cipher_fi 59.000s 10014.125us 336 350 96.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 34.000s 8488.366us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:910) scoreboard [scoreboard]
aes_fi 115189047353685149966219462131325038005758632847089211731497790060222505548078 12934
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
Job killed!
aes_stress_all 6197877989226701448332349725821711967057655486190576120512867053823305448368 None
aes_cipher_fi 80861937096122041101730877168753601842628175910392361526086204590355533837127 None
aes_control_fi 23265178886601881879609058860208823741909793694529087992683890190568585559166 None
aes_control_fi 61343463153350708837747825927020429916826905830965880532099490523299897037488 None
aes_control_fi 58928126487776160592109299100513103117559318717095835473994191898519890563664 None
aes_cipher_fi 44858237102406154447489956019851578897052084237693554472841794571202557753419 None
aes_cipher_fi 22434712082590672247768361608791951418866159596597173965828909511086740688051 None
aes_cipher_fi 32696397375597214823724371278081961323076300205964953770042558488863288667119 None
aes_control_fi 62867788804339934193238930509329993866588358101284444695913031754134975677947 None
aes_cipher_fi 58878911670601113852182744014358080671849781354070447693981898297547294424474 None
aes_control_fi 85878516953367736824664144920452041286972561857144779679300320766924803204696 None
aes_control_fi 75585240505777419410134523338344219821728535973477129950141672745291490940213 None
aes_control_fi 12054298469814315838808361482419281474873762759909469277061233342232029915981 None
aes_control_fi 20053865766803973677879902647579161445063793351361746049207794886201104459478 None
aes_control_fi 31927692379871892968827555515372686341529725555355611925320082542912144911306 None
aes_control_fi 108742544697562856034028121245011092239018234339818070345073620465087584250383 None
aes_control_fi 24240015417126638716299095499655175055693412726887620994852831366987827973879 None
aes_cipher_fi 21981435862034376073064224537183995718191732399514919740663223817909132077613 None
aes_control_fi 111901948782970752543534681727477710924355963558849476763340143534072827595922 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 77405877061550367860773349205919831826618017059026259521574590744059816719472 268
UVM_INFO @ 8488365816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 21551717059330894602183863069883649933494626566326974797337022696118919744613 388
UVM_INFO @ 648617428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 9982055419587954270927977044837116501911483693659079160200770921309933234888 603
UVM_INFO @ 1504610564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 82847957143614574334726301293093710638447521088010657860554617526346186097425 268
UVM_INFO @ 48002598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 34161795589948196884753642280972112997187089717583530233716138721959011952613 326
UVM_INFO @ 1461748743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 80103905490772498230016325633905436496482305853683600207865279595019383562210 143
UVM_INFO @ 10018117831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 43503162604759013548067037057881294159010333883271625621015135193261097884786 147
UVM_INFO @ 10018498049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 87171198019154473925310592043827393647817883561182863595094468859231404885555 146
UVM_INFO @ 10028477753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 48605637325871300725326390932216550371442030608211023590285828127265905942031 148
UVM_INFO @ 10062879584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 101934505034160046793587365642247686483327567562403202692368626094274831067463 151
UVM_INFO @ 10007468944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 4537012980833630322338954163330669200199896803130375139765765599750284084399 153
UVM_INFO @ 10003580506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 96063871007429860696366847358000436455706613178086909107472601142411462495273 144
UVM_INFO @ 10018727906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 95344503918769300387657568236503154441746056865408341434205366585513908811108 523
UVM_INFO @ 244493396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 2600562662057712311137474225396966187417561011857277078204316210416428036793 220
UVM_INFO @ 121227513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 9373650902581582290595317350045255572568092922985028839262885695877917911510 524
UVM_INFO @ 277346710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 65516863934809654146698510307086722095717754077057403907105085223094951594370 359
UVM_INFO @ 1634661714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 32689540788070381691241941457815001605195978878353702950725836474595659981511 163
UVM_INFO @ 108387736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '*' in file '/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_*/aes_scoreboard.sv' at time * PS + *.
aes_sideload 70731291436553170726156135227548919354635770947542440497805662630872386506387 9571
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '738' in file '/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 27344826 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '738' in file '/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 27344826 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '738' in file '/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 27344826 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '738' in file '/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 27344826 PS + 10.
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 47333238649325060600738415256553253814576095959499372615952283827339628049950 153
UVM_INFO @ 10025195922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 67333723907731447682443433297674058609092338692070612334078575987574136183043 150
UVM_INFO @ 10014125014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 29089161431241104278311369885269006046063598305612226141338410177260046151536 142
UVM_INFO @ 10025410754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 21538909905687781252483993577421495371478226531712640427728890805063154088857 152
UVM_INFO @ 10005562503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 40809373072349280352820727683045149917612220959189872985962942090945366926157 144
UVM_INFO @ 10025597466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 100893807483488802407366728012296640964667420553521142073370732647152519655260 154
UVM_INFO @ 10008244682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 35851990127868089829852844976134332787685476932281384619007554146367194246481 153
UVM_INFO @ 10010690103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 30770785387475616167422610815785346356435418089429831214395046383891536620656 150
UVM_INFO @ 10008034359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_cipher_fi 115157001682018668990095285423625662688136394868296190508506359412567702607891 148
UVM_INFO @ 23715167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---