Simulation Results: aes/unmasked

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.39 %
  • code
  • 94.97 %
  • assert
  • 98.13 %
  • func
  • 93.06 %
  • block
  • 95.61 %
  • line
  • 97.27 %
  • branch
  • 90.92 %
  • toggle
  • 98.08 %
  • FSM
  • 93.62 %
Validation stages
V1
100.00%
V2
99.12%
V2S
96.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 99.733us 1 1 100.00
smoke 50 50 100.00
aes_smoke 4.000s 168.139us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 88.352us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 2.000s 57.169us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 6.000s 188.862us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 4.000s 513.264us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 370.819us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 2.000s 57.169us 20 20 100.00
aes_csr_aliasing 4.000s 513.264us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 4.000s 168.139us 50 50 100.00
aes_config_error 4.000s 424.727us 50 50 100.00
aes_stress 4.000s 116.374us 50 50 100.00
key_length 150 150 100.00
aes_smoke 4.000s 168.139us 50 50 100.00
aes_config_error 4.000s 424.727us 50 50 100.00
aes_stress 4.000s 116.374us 50 50 100.00
back2back 100 100 100.00
aes_stress 4.000s 116.374us 50 50 100.00
aes_b2b 8.000s 955.692us 50 50 100.00
backpressure 50 50 100.00
aes_stress 4.000s 116.374us 50 50 100.00
multi_message 198 200 99.00
aes_smoke 4.000s 168.139us 50 50 100.00
aes_config_error 4.000s 424.727us 50 50 100.00
aes_stress 4.000s 116.374us 50 50 100.00
aes_alert_reset 4.000s 363.185us 48 50 96.00
failure_test 148 150 98.67
aes_man_cfg_err 3.000s 232.377us 50 50 100.00
aes_config_error 4.000s 424.727us 50 50 100.00
aes_alert_reset 4.000s 363.185us 48 50 96.00
trigger_clear_test 49 50 98.00
aes_clear 4.000s 220.243us 49 50 98.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 114.486us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 188.948us 1 1 100.00
reset_recovery 48 50 96.00
aes_alert_reset 4.000s 363.185us 48 50 96.00
stress 50 50 100.00
aes_stress 4.000s 116.374us 50 50 100.00
sideload 100 100 100.00
aes_stress 4.000s 116.374us 50 50 100.00
aes_sideload 3.000s 112.746us 50 50 100.00
deinitialization 49 50 98.00
aes_deinit 5.000s 240.419us 49 50 98.00
stress_all 8 10 80.00
aes_stress_all 196.000s 10002.669us 8 10 80.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 3.000s 71.742us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 3.000s 55.925us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 3.000s 147.945us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 3.000s 147.945us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 88.352us 5 5 100.00
aes_csr_rw 2.000s 57.169us 20 20 100.00
aes_csr_aliasing 4.000s 513.264us 5 5 100.00
aes_same_csr_outstanding 3.000s 134.154us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 88.352us 5 5 100.00
aes_csr_rw 2.000s 57.169us 20 20 100.00
aes_csr_aliasing 4.000s 513.264us 5 5 100.00
aes_same_csr_outstanding 3.000s 134.154us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 8.000s 372.408us 50 50 100.00
fault_inject 659 700 94.14
aes_fi 4.000s 83.866us 50 50 100.00
aes_control_fi 39.000s 10002.501us 282 300 94.00
aes_cipher_fi 43.000s 10020.863us 327 350 93.43
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 194.306us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 194.306us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 194.306us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 194.306us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 344.049us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 5.000s 1105.351us 5 5 100.00
aes_tl_intg_err 3.000s 317.255us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 3.000s 317.255us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 48 50 96.00
aes_alert_reset 4.000s 363.185us 48 50 96.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 194.306us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 194.306us 20 20 100.00
sec_cm_main_config_sparse 213 220 96.82
aes_smoke 4.000s 168.139us 50 50 100.00
aes_stress 4.000s 116.374us 50 50 100.00
aes_alert_reset 4.000s 363.185us 48 50 96.00
aes_core_fi 307.000s 200000.000us 65 70 92.86
sec_cm_gcm_config_sparse 265 270 98.15
aes_gcm_save_restore 3.000s 71.742us 100 100 100.00
aes_config_error 4.000s 424.727us 50 50 100.00
aes_stress 4.000s 116.374us 50 50 100.00
aes_core_fi 307.000s 200000.000us 65 70 92.86
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 194.306us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 98.000us 50 50 100.00
aes_stress 4.000s 116.374us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 4.000s 116.374us 50 50 100.00
aes_sideload 3.000s 112.746us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 98.000us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 98.000us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 98.000us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 98.000us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 98.000us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 4.000s 116.374us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 4.000s 116.374us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 4.000s 83.866us 50 50 100.00
sec_cm_main_fsm_redun 709 750 94.53
aes_fi 4.000s 83.866us 50 50 100.00
aes_control_fi 39.000s 10002.501us 282 300 94.00
aes_cipher_fi 43.000s 10020.863us 327 350 93.43
aes_ctr_fi 3.000s 72.530us 50 50 100.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 4.000s 83.866us 50 50 100.00
sec_cm_cipher_fsm_redun 659 700 94.14
aes_fi 4.000s 83.866us 50 50 100.00
aes_control_fi 39.000s 10002.501us 282 300 94.00
aes_cipher_fi 43.000s 10020.863us 327 350 93.43
sec_cm_cipher_ctr_redun 327 350 93.43
aes_cipher_fi 43.000s 10020.863us 327 350 93.43
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 4.000s 83.866us 50 50 100.00
sec_cm_ctr_fsm_redun 382 400 95.50
aes_fi 4.000s 83.866us 50 50 100.00
aes_control_fi 39.000s 10002.501us 282 300 94.00
aes_ctr_fi 3.000s 72.530us 50 50 100.00
sec_cm_ghash_fsm_sparse 50 50 100.00
aes_fi 4.000s 83.866us 50 50 100.00
sec_cm_ctrl_sparse 709 750 94.53
aes_fi 4.000s 83.866us 50 50 100.00
aes_control_fi 39.000s 10002.501us 282 300 94.00
aes_cipher_fi 43.000s 10020.863us 327 350 93.43
aes_ctr_fi 3.000s 72.530us 50 50 100.00
sec_cm_main_fsm_global_esc 48 50 96.00
aes_alert_reset 4.000s 363.185us 48 50 96.00
sec_cm_main_fsm_local_esc 709 750 94.53
aes_fi 4.000s 83.866us 50 50 100.00
aes_control_fi 39.000s 10002.501us 282 300 94.00
aes_cipher_fi 43.000s 10020.863us 327 350 93.43
aes_ctr_fi 3.000s 72.530us 50 50 100.00
sec_cm_cipher_fsm_local_esc 709 750 94.53
aes_fi 4.000s 83.866us 50 50 100.00
aes_control_fi 39.000s 10002.501us 282 300 94.00
aes_cipher_fi 43.000s 10020.863us 327 350 93.43
aes_ctr_fi 3.000s 72.530us 50 50 100.00
sec_cm_ctr_fsm_local_esc 382 400 95.50
aes_fi 4.000s 83.866us 50 50 100.00
aes_control_fi 39.000s 10002.501us 282 300 94.00
aes_ctr_fi 3.000s 72.530us 50 50 100.00
sec_cm_ghash_fsm_local_esc 139 140 99.29
aes_fi 4.000s 83.866us 50 50 100.00
aes_ghash_fi 31.000s 10010.357us 89 90 98.89
sec_cm_data_reg_local_esc 659 700 94.14
aes_fi 4.000s 83.866us 50 50 100.00
aes_control_fi 39.000s 10002.501us 282 300 94.00
aes_cipher_fi 43.000s 10020.863us 327 350 93.43
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 28.000s 6907.282us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 82748065650027665611203109602912687081148524491770070100099143694192428234452 1211
UVM_INFO @ 1501473559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 94786277700700787321884846163944835296712394127433579510768354961020684520642 1708
UVM_INFO @ 6907281769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 22374040359395725508309541224878574639117322020457930856305994952340647948944 257
UVM_INFO @ 57120203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 53367397180453733896364806630904986890636163233459019102884449255323893064412 426
UVM_INFO @ 296159983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 114143837241487822177322192204056618637197136013971412684418946517575604065844 195
UVM_INFO @ 60262046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
aes_control_fi 40076175463856261363085511273113177982897790554309875649710833260508907469936 None
aes_control_fi 72750552286097919969495207664182124287526793177852911432455182616555871192768 None
aes_cipher_fi 110472678808584745611936431247636758132350694235833796465752583638137353340591 None
aes_deinit 78267743739448071578818162258421875621397203682140549598054070469118881590415 None
aes_control_fi 11658234532701624502095091707489062179556526129282435719684273212339636581595 None
aes_cipher_fi 80950761302209979032767288869649278510407002198799255090028933782149834419995 None
aes_cipher_fi 102698986730694340609471462774249575788992853922620256517951327743313467520685 None
aes_control_fi 73875616915626383598136754439185186307005064431533031619104888158726490090884 None
aes_control_fi 69962262820719832113880470132074827323461789704997099691705335200047272423008 None
aes_cipher_fi 93435333623604940936282099436575597499856140973575756701801356491896347033271 None
aes_cipher_fi 38155145401805422401449260953852506657881698502224965844038983621877415372051 None
aes_cipher_fi 12557126675100782471529043317696841325985833340026019135618642952391218051240 None
aes_control_fi 111508454388282917638131685323511780078295319811263676214137104014598831227844 None
aes_cipher_fi 55500321237100338487961844340440712700279058763143448529219610731315196819384 None
aes_cipher_fi 111139152683431736114060052734024215961928248172321481069262847507061798286060 None
aes_control_fi 64177173692304299947997887443337295991234016666996957988207493075237724928214 None
aes_control_fi 22697040489029719961661810567162668018271086220297479504094241845956197374736 None
aes_control_fi 70014211626625264409051524989047453556910467114336891596894235288485800275147 None
aes_control_fi 31626245782174878813431981449596709227766346746814302718364367250877934413964 None
aes_control_fi 24566401973134077814719123464411486002097016677509457416564846361928159756138 None
aes_cipher_fi 88855486091834746349322908097396654048629507443426062133998911041383444533773 None
aes_cipher_fi 114185653169404906183358461633773557397059890234543684508607230169014224466861 None
aes_cipher_fi 67864561394715307608469008809747481686036369298693136589938946583226079196052 None
aes_cipher_fi 81518323780130376928793929660666676128940837172539406395657578790673825904116 None
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_alert_reset_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG
aes_stress_all_with_rand_reset 22889287213286453569963203453027268054174690705761895768412869908795806699962 426
UVM_INFO @ 1633328907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1136): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS)
aes_alert_reset 12478701243345892923668388825957213817182230314660203120375532824477466841649 1290
UVM_ERROR @ 15851771 ps: (aes_core.sv:1136) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_INFO @ 15851771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 68174135661559616888909660258329732705971954522133556823597875980828477765697 275
UVM_INFO @ 2111745499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
aes_stress_all 38579216862330019858317286449810514130376815831773871281326425000097746516439 1096917
UVM_INFO @ 10002668562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_ghash_fi 78528995452650108135454351056813866309858406157582744146941543295224318557482 142
UVM_INFO @ 10010356936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 7893089214500124694263227314449305256890427369409763657522071353874448947115 144
UVM_INFO @ 10020863159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_reseed_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT
aes_stress_all_with_rand_reset 20602223833396779273394214343381183197498533860962054908853103871792224798235 633
UVM_INFO @ 1456694699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 24045457649358510278359084001147762915153575592035972244875866561841380980077 150
UVM_INFO @ 10005429812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 58343516758293382297175795621332741657211644130884572892593607218390442207543 147
UVM_INFO @ 10012833051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 76068945895770370567782356786013254356779582697419268527144761944781649299247 172
UVM_INFO @ 96850530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1142): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS)
aes_stress_all_with_rand_reset 97326110453782233072531422680629814181471131021551476254993960388759274333828 390
UVM_ERROR @ 262233939 ps: (aes_core.sv:1142) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 262233939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:775) scoreboard [scoreboard] # *
aes_stress_all 83014377294011130543409389995828670673807066419011429185468461152309329197165 64233
TEST FAILED MESSAGES DID NOT MATCH
0 32 3c 00 0
1 00 b0 00 0
aes_alert_reset 21277233105249725396242192687334106083578703190513558024097611667710895198522 3635
TEST FAILED MESSAGES DID NOT MATCH
0 d4 64 00 0
1 00 ab 00 0
aes_clear 30686744866410072235416423092425402093252425181820319402101495608387664148239 1356
TEST FAILED MESSAGES DID NOT MATCH
0 6b e2 92 0
1 17 b0 59 0
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
aes_core_fi 51915421216695586876695544721991871346422739791500851845220373715860008904826 162
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 58051812556210858229253043851396334947045596052054710239987763333823436719062 148
UVM_INFO @ 10012134933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
aes_core_fi 35248772590359337013118515329430980478052376224387477048197238613531043340813 141
UVM_INFO @ 10021545497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 22473337599285993491484290219723655015699764833315288141614217282004251252498 160
UVM_INFO @ 10003020714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 99195749223612622214695877658482034684338946310856814401059613838377933207426 148
UVM_INFO @ 10005155440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 29435268283069558767808366321646118797499040330769405795185421141763184767777 147
UVM_INFO @ 10013109702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 83006466185463972741462948060437107678941132706626534421418636577382122462429 154
UVM_INFO @ 10011677379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 33295255288008752074255461681341833563686789803822031823016211900162287311705 148
UVM_INFO @ 10014797745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 17352378196826838446257734039390117703901778532577021904736432656772605365814 155
UVM_INFO @ 10014049278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 83099262913106348186902138111685269813708737380948699020868162998016306905943 145
UVM_INFO @ 10007534660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 101156913609725690932247426689055254755900446425076434829638641423982493496603 145
UVM_INFO @ 10029739717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 2399477437788688818023233429150780701311940757549274619319729847311474868251 159
UVM_INFO @ 10008190883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 44520082319627430468355410688137850658607774799509821316427217510907353719989 154
UVM_INFO @ 10019244943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 72444719287810697105803467491999272245392243301337475935621452544982974256525 146
UVM_INFO @ 10015277667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 95332078851868135339463653204720263740868407330607303602356008227486958895271 152
UVM_INFO @ 10002500965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 15048979305286916137351369169838161284091868046933389867871626159480670430394 145
UVM_INFO @ 10010155782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 13890516328044980114202089189393697952170607336237079771920019946279884016452 149
UVM_INFO @ 10007843627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 11392286263278249047572263504740247633794454394050584094770726677071125675479 147
UVM_INFO @ 10008669132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 81073315662445568153296239576256236685121082634330232968664227482821517209406 146
UVM_INFO @ 10011140785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 61477625296073325283951960988288922388237075440998680104121511637956843108101 153
UVM_INFO @ 10009240114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---