Simulation Results: alert_handler

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.99 %
  • code
  • 98.91 %
  • assert
  • 98.88 %
  • func
  • 99.19 %
  • line
  • 99.99 %
  • branch
  • 99.99 %
  • cond
  • 97.46 %
  • toggle
  • 97.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
94.23%
V2S
98.11%
V3
52.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
alert_handler_smoke 63.480s 2413.751us 50 50 100.00
csr_hw_reset 5 5 100.00
alert_handler_csr_hw_reset 7.990s 674.837us 5 5 100.00
csr_rw 20 20 100.00
alert_handler_csr_rw 11.170s 413.913us 20 20 100.00
csr_bit_bash 5 5 100.00
alert_handler_csr_bit_bash 395.970s 94863.300us 5 5 100.00
csr_aliasing 5 5 100.00
alert_handler_csr_aliasing 204.720s 6415.393us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
alert_handler_csr_mem_rw_with_rand_reset 14.060s 594.414us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
alert_handler_csr_rw 11.170s 413.913us 20 20 100.00
alert_handler_csr_aliasing 204.720s 6415.393us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 50 50 100.00
alert_handler_esc_alert_accum 265.920s 17236.940us 50 50 100.00
esc_timeout 50 50 100.00
alert_handler_esc_intr_timeout 72.820s 1464.172us 50 50 100.00
entropy 50 50 100.00
alert_handler_entropy 2492.900s 57338.898us 50 50 100.00
sig_int_fail 47 50 94.00
alert_handler_sig_int_fail 56.090s 3614.455us 47 50 94.00
clk_skew 50 50 100.00
alert_handler_smoke 63.480s 2413.751us 50 50 100.00
random_alerts 50 50 100.00
alert_handler_random_alerts 65.660s 17543.045us 50 50 100.00
random_classes 50 50 100.00
alert_handler_random_classes 51.210s 1170.179us 50 50 100.00
ping_timeout 16 50 32.00
alert_handler_ping_timeout 503.780s 15760.311us 16 50 32.00
lpg 97 100 97.00
alert_handler_lpg 2816.270s 239697.205us 48 50 96.00
alert_handler_lpg_stub_clk 2527.260s 115388.090us 49 50 98.00
stress_all 49 50 98.00
alert_handler_stress_all 2927.210s 236033.056us 49 50 98.00
alert_handler_entropy_stress_test 20 20 100.00
alert_handler_entropy_stress 52.350s 1264.597us 20 20 100.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 4.820s 94.565us 20 20 100.00
intr_test 50 50 100.00
alert_handler_intr_test 3.470s 52.011us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
alert_handler_tl_errors 26.600s 1627.421us 20 20 100.00
tl_d_illegal_access 20 20 100.00
alert_handler_tl_errors 26.600s 1627.421us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
alert_handler_csr_hw_reset 7.990s 674.837us 5 5 100.00
alert_handler_csr_rw 11.170s 413.913us 20 20 100.00
alert_handler_csr_aliasing 204.720s 6415.393us 5 5 100.00
alert_handler_same_csr_outstanding 44.840s 544.524us 20 20 100.00
tl_d_partial_access 50 50 100.00
alert_handler_csr_hw_reset 7.990s 674.837us 5 5 100.00
alert_handler_csr_rw 11.170s 413.913us 20 20 100.00
alert_handler_csr_aliasing 204.720s 6415.393us 5 5 100.00
alert_handler_same_csr_outstanding 44.840s 544.524us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
alert_handler_shadow_reg_errors 308.530s 5752.288us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
alert_handler_shadow_reg_errors 308.530s 5752.288us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
alert_handler_shadow_reg_errors 308.530s 5752.288us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
alert_handler_shadow_reg_errors 308.530s 5752.288us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1115.480s 23232.776us 20 20 100.00
tl_intg_err 25 25 100.00
alert_handler_sec_cm 23.240s 491.297us 5 5 100.00
alert_handler_tl_intg_err 77.440s 4950.972us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
alert_handler_tl_intg_err 77.440s 4950.972us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
alert_handler_shadow_reg_errors 308.530s 5752.288us 20 20 100.00
sec_cm_ping_timer_config_regwen 50 50 100.00
alert_handler_smoke 63.480s 2413.751us 50 50 100.00
sec_cm_alert_config_regwen 50 50 100.00
alert_handler_smoke 63.480s 2413.751us 50 50 100.00
sec_cm_alert_loc_config_regwen 50 50 100.00
alert_handler_smoke 63.480s 2413.751us 50 50 100.00
sec_cm_class_config_regwen 50 50 100.00
alert_handler_smoke 63.480s 2413.751us 50 50 100.00
sec_cm_alert_intersig_diff 47 50 94.00
alert_handler_sig_int_fail 56.090s 3614.455us 47 50 94.00
sec_cm_lpg_intersig_mubi 48 50 96.00
alert_handler_lpg 2816.270s 239697.205us 48 50 96.00
sec_cm_esc_intersig_diff 47 50 94.00
alert_handler_sig_int_fail 56.090s 3614.455us 47 50 94.00
sec_cm_alert_rx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 2492.900s 57338.898us 50 50 100.00
sec_cm_esc_tx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 2492.900s 57338.898us 50 50 100.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 23.240s 491.297us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 23.240s 491.297us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 23.240s 491.297us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 23.240s 491.297us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 23.240s 491.297us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 23.240s 491.297us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 23.240s 491.297us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 23.240s 491.297us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 23.240s 491.297us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 50 52.00
alert_handler_stress_all_with_rand_reset 405.360s 7672.846us 26 50 52.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 87681104271189991412915960790977708283629459752808516165868738193482784167789 84
UVM_INFO @ 3973652018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 79599904001194529808385908617782781805931086857203241948580156341991586207777 102
UVM_INFO @ 18200640632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 86933918763500461800647056172185569431946706781312388002868703876071127892553 111
UVM_INFO @ 4680940576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 70834599135401401365707343841965412351998854538005936550909965873136090186876 106
UVM_INFO @ 10489229176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 75102866207865816250303365666065979591900346459078681093933888032400840902282 80
UVM_INFO @ 49372509105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 16876373636924655097021939608051891038252007053447744346363868028514693104540 105
UVM_INFO @ 8962643717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 75527659093380660290480240128752775098165145961953857781240309097479885261649 120
UVM_INFO @ 9626573166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 14983873895941977768058228622512104409337619713565374879397926572414605946397 105
UVM_INFO @ 20004394053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 41831988725064164318450754859259395909736064701593030490784501817967960717241 141
UVM_INFO @ 39523415191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 62966346575310442655896681602028946432393021081642707486115245668061331865009 84
UVM_INFO @ 1498695817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 99724542258212533123449268702334093807413003509822468859479842595428424911893 137
UVM_INFO @ 9777104931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 114125736050725271643848063206015977556537195398010880672814887781959517611547 82
UVM_INFO @ 58540768220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 13816502345863468514005233958231853343325008552890806321726544405363718646345 84
UVM_INFO @ 2944295844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 47980637757486131948908079670114440215550230266129767920258251041427061473677 93
UVM_INFO @ 10551169153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 15187711676462537966421283395298002978583894719380084049974875352307818917546 99
UVM_INFO @ 83732597702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 65699698234530015351051585315894944515456489916870176789303433145214607424079 115
UVM_INFO @ 8214684222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 88191109829204527221101991840293145725777806354654051630413352355243621030521 93
UVM_INFO @ 10933129105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 43874986105806371344836014361960683602031862263790652365312899156034365518827 108
UVM_INFO @ 7406405606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 34606995765911045009414973152151704614846271276292652257763813365654860437816 87
UVM_INFO @ 1012948167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 97534498466297939550950224622631907586426113907599882554170170058674481505866 102
UVM_INFO @ 3284951483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 3115377606451452247175881927587740694416006811823577526357038263195334822242 111
UVM_INFO @ 23518506085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 72469608649131953241850372449268740060231309592817261782629606469618481401184 111
UVM_INFO @ 4278611826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 51182676820808792094550719638996698296334506715406182719533226068642034796388 111
UVM_INFO @ 24183876545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 14196849387245652945926226139523750486270808271713344038112674960650498621623 102
UVM_INFO @ 8632856644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 27741023118331367089413545530828229083395185170633969269337195969651850389810 120
UVM_INFO @ 6978376856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 31866597760748825344253166255353328943490547475917545601548842198734494482954 90
UVM_INFO @ 5944566101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 41774789567434379169687237595665903607800478940923585525363872734755814386576 84
UVM_INFO @ 1191515429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 103277130873825025977848392745565784901206476092069127378301164432218975753413 114
UVM_INFO @ 5269826074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:598) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 40475237933578585653511366196559193858909351650435701545760055947419433754245 83
UVM_INFO @ 3824850860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 104249342118356693477624660429638321923477498062572405409820139814993088884404 80
UVM_INFO @ 183196777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 63537406615114569336876398721856272261480382392468040597154843791142883605556 80
UVM_INFO @ 198728251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 51371258683896423188851054789003887218876412945767515385197881489475987502808 80
UVM_INFO @ 435662795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 95507605738194329861935139365786984563277683698274885293369387991682036016227 80
UVM_INFO @ 464585567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 14681804064363285311691125672442512922358685847866753138835049488016319737481 80
UVM_INFO @ 1153616660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 10480731182760296163515550917783691429144551267610787967842977559479039710431 80
UVM_INFO @ 1865449579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 9740571685704233736398607473435282503211630412034765775922603695175335913241 80
UVM_INFO @ 1337721898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
alert_handler_stress_all_with_rand_reset 86136609387131675350411400042799404913018044867099798547963733723752018478183 164
UVM_INFO @ 1184308546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 8402848960073235693369531321046096356276869535315439672756412377622413569026 135
UVM_INFO @ 6047151448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertPingFail)
alert_handler_lpg_stub_clk 46262007950437209807365420698648662235852944210985501430282409876394891694142 81
UVM_INFO @ 63498501385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 57236534700060199189699308456119762881151519107695788754720569600346580883525 198
UVM_INFO @ 4617800211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 74259096645532168379147534066340355420849449852394738107130067644707992888791 89
UVM_INFO @ 3879278185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 45604785490787664957242926508173637033439363894634358136758727893471516086696 103
UVM_INFO @ 640408254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 11352029387061018824953248987461480583706941806968992386526651705945481222107 91
UVM_INFO @ 3725834226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 60038471238048482142782776942460994190507687499800083179212755636685109813415 247
UVM_INFO @ 5769572897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 40684187048277617388377498352890401519523120042233049506028159402782294524844 84
UVM_INFO @ 795286406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 104045514675088283509336499642468826961815290988123021051112743197917687619339 94
UVM_INFO @ 661609579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 72440246556308542431956861693407057823934610444867551218836372095424260316403 119
UVM_INFO @ 1487393924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 72619022725960562965126632525296982404819906592292241146750740148666589382902 120
UVM_INFO @ 1027993699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 50115316887854842400952018439519154912164034479160746318366921017175769900090 225
UVM_INFO @ 16706666368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 66465303230743209653579137473173823333938035540543569208606553820804759326476 85
UVM_INFO @ 101664817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 77773404260572508082661145275672458847282924047936384287628806334644393844296 88
UVM_INFO @ 4115962476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 22376278588415917289717029627380771500786076477409778982987481999484533354520 95
UVM_INFO @ 1536504371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 10396060545772998180781216495797681266665618126382715262417735389109748371366 137
UVM_INFO @ 10040778392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 72274165638363784329808853699180294631967462234426170870619919159789003866544 99
UVM_INFO @ 1052526633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 44616342598493552855201113156006627060715564366316896227048524446081404080088 91
UVM_INFO @ 2661736193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 95769448256246421792191481259545874428032298335622338314338699090034526614770 83
UVM_INFO @ 434146459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 39691988639843933570719118930239164543427188758762093227308358472412922613085 95
UVM_INFO @ 1089940798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 40076813552777734579172569273499897020645859457085992750888659352921717997511 140
UVM_INFO @ 1633906132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 31888037378669029223431424736797361800045948417702769627302216239850877046265 106
UVM_INFO @ 22633780605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 4574081360684109288382856864303217448677442533158568778388992313148678122551 125
UVM_INFO @ 3779082819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail)
alert_handler_stress_all 92739221084756031380603948929143329244323458163496119845272480531270448856322 198
UVM_INFO @ 63048049007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_sig_int_fail 115614685223344667447970619503478665936848112775907680009692724628283998009692 85
UVM_INFO @ 1717061614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_sig_int_fail 4206941871543564292342693582461469614968804158011192422711372595457200049794 84
UVM_INFO @ 3130984904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_sig_int_fail 37601134724429650938619099178216085895841888999220854168734703346095137404839 82
UVM_INFO @ 153186141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state
alert_handler_stress_all_with_rand_reset 29835446187582083872867877150510339053050962272788975849798897637114600516322 84
UVM_INFO @ 138829734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---