Simulation Results: chip

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.40 %
  • code
  • 85.97 %
  • assert
  • 97.87 %
  • func
  • 99.37 %
  • line
  • 94.65 %
  • branch
  • 93.85 %
  • cond
  • 92.60 %
  • toggle
  • 91.61 %
  • FSM
  • 57.14 %
Validation stages
V1
94.55%
V2
92.89%
V2S
50.00%
V3
83.65%
unmapped
68.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 12 12 100.00
chip_sw_example_flash 246.510s 3252.721us 3 3 100.00
chip_sw_example_rom 108.630s 2452.211us 3 3 100.00
chip_sw_example_manufacturer 200.480s 3375.496us 3 3 100.00
chip_sw_example_concurrency 222.550s 2843.927us 3 3 100.00
csr_hw_reset 5 5 100.00
chip_csr_hw_reset 406.150s 6756.764us 5 5 100.00
csr_rw 20 20 100.00
chip_csr_rw 639.380s 5615.195us 20 20 100.00
csr_bit_bash 5 5 100.00
chip_csr_bit_bash 788.550s 7172.506us 5 5 100.00
csr_aliasing 5 5 100.00
chip_csr_aliasing 5351.350s 27482.479us 5 5 100.00
csr_mem_rw_with_rand_reset 8 20 40.00
chip_csr_mem_rw_with_rand_reset 820.830s 10824.073us 8 20 40.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
chip_csr_aliasing 5351.350s 27482.479us 5 5 100.00
chip_csr_rw 639.380s 5615.195us 20 20 100.00
xbar_smoke 100 100 100.00
xbar_smoke 12.180s 239.226us 100 100 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 430.280s 4422.769us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 430.280s 4422.769us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 430.280s 4422.769us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 533.090s 5024.672us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 533.090s 5024.672us 5 5 100.00
chip_sw_uart_tx_rx_idx1 456.260s 4178.444us 5 5 100.00
chip_sw_uart_tx_rx_idx2 559.450s 5059.107us 5 5 100.00
chip_sw_uart_tx_rx_idx3 536.640s 5143.733us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 2391.270s 13260.467us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1549.970s 8780.070us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1379.180s 13149.373us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 10 10 100.00
chip_padctrl_attributes 304.910s 6071.360us 10 10 100.00
chip_padctrl_attributes 10 10 100.00
chip_padctrl_attributes 304.910s 6071.360us 10 10 100.00
chip_sw_sleep_pin_mio_dio_val 1 3 33.33
chip_sw_sleep_pin_mio_dio_val 277.370s 3421.554us 1 3 33.33
chip_sw_sleep_pin_wake 3 3 100.00
chip_sw_sleep_pin_wake 441.880s 6318.054us 3 3 100.00
chip_sw_sleep_pin_retention 3 3 100.00
chip_sw_sleep_pin_retention 304.880s 4701.558us 3 3 100.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1187.860s 14704.932us 5 5 100.00
chip_tap_straps_testunlock0 401.540s 6410.388us 5 5 100.00
chip_tap_straps_rma 572.630s 9171.418us 5 5 100.00
chip_tap_straps_prod 1728.410s 17770.146us 5 5 100.00
chip_sw_pattgen_ios 3 3 100.00
chip_sw_pattgen_ios 279.280s 3520.393us 3 3 100.00
chip_sw_sleep_pwm_pulses 3 3 100.00
chip_sw_sleep_pwm_pulses 1077.250s 8812.697us 3 3 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 599.980s 6682.741us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 599.980s 6682.741us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 832.230s 7986.263us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 1706.690s 14310.346us 0 3 0.00
chip_sw_ast_sys_clk_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 496.120s 4613.648us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 849.500s 6143.121us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4475.290s 20777.435us 3 3 100.00
chip_sw_aes_enc_jitter_en 246.660s 3261.449us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1044.900s 7049.247us 3 3 100.00
chip_sw_hmac_enc_jitter_en 234.160s 3159.549us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1662.240s 12264.526us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 275.330s 3570.190us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 545.750s 5372.152us 3 3 100.00
chip_sw_clkmgr_jitter 197.680s 3159.240us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 225.170s 3314.204us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 6 8 75.00
chip_sw_sensor_ctrl_alert 824.840s 8195.645us 3 5 60.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 338.540s 5279.823us 3 3 100.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 196.150s 2993.459us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 338.540s 5279.823us 3 3 100.00
chip_sw_smoketest 51 51 100.00
chip_sw_flash_scrambling_smoketest 194.060s 3382.903us 3 3 100.00
chip_sw_aes_smoketest 274.990s 3516.628us 3 3 100.00
chip_sw_aon_timer_smoketest 242.600s 3174.558us 3 3 100.00
chip_sw_clkmgr_smoketest 238.190s 2635.223us 3 3 100.00
chip_sw_csrng_smoketest 195.590s 3139.393us 3 3 100.00
chip_sw_entropy_src_smoketest 1182.930s 7718.539us 3 3 100.00
chip_sw_gpio_smoketest 289.040s 3006.651us 3 3 100.00
chip_sw_hmac_smoketest 287.020s 3199.959us 3 3 100.00
chip_sw_kmac_smoketest 287.980s 3244.456us 3 3 100.00
chip_sw_otbn_smoketest 1174.080s 7411.163us 3 3 100.00
chip_sw_pwrmgr_smoketest 453.160s 6923.223us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 410.780s 6556.464us 3 3 100.00
chip_sw_rv_plic_smoketest 238.700s 2931.911us 3 3 100.00
chip_sw_rv_timer_smoketest 213.340s 2821.975us 3 3 100.00
chip_sw_rstmgr_smoketest 156.000s 2916.520us 3 3 100.00
chip_sw_sram_ctrl_smoketest 241.970s 2700.023us 3 3 100.00
chip_sw_uart_smoketest 203.990s 2873.708us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 216.560s 2911.817us 3 3 100.00
chip_sw_rom_functests 0 3 0.00
rom_keymgr_functest 433.270s 5536.549us 0 3 0.00
chip_sw_boot 3 3 100.00
chip_sw_uart_tx_rx_bootstrap 12667.550s 65410.698us 3 3 100.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 3779.970s 14628.145us 3 3 100.00
chip_sw_rom_raw_unlock 2 3 66.67
rom_raw_unlock 803.820s 16537.127us 2 3 66.67
chip_sw_power_idle_load 0 3 0.00
chip_sw_power_idle_load 253.780s 3974.046us 0 3 0.00
chip_sw_power_sleep_load 0 3 0.00
chip_sw_power_sleep_load 262.660s 3369.895us 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 3 3 100.00
chip_sw_exit_test_unlocked_bootstrap 11271.380s 56017.767us 3 3 100.00
chip_sw_inject_scramble_seed 3 3 100.00
chip_sw_inject_scramble_seed 11301.930s 59249.841us 3 3 100.00
tl_d_oob_addr_access 6 30 20.00
chip_tl_errors 419.990s 5311.954us 6 30 20.00
tl_d_illegal_access 6 30 20.00
chip_tl_errors 419.990s 5311.954us 6 30 20.00
tl_d_outstanding_access 50 50 100.00
chip_csr_aliasing 5351.350s 27482.479us 5 5 100.00
chip_same_csr_outstanding 3914.280s 31946.853us 20 20 100.00
chip_csr_hw_reset 406.150s 6756.764us 5 5 100.00
chip_csr_rw 639.380s 5615.195us 20 20 100.00
tl_d_partial_access 50 50 100.00
chip_csr_aliasing 5351.350s 27482.479us 5 5 100.00
chip_same_csr_outstanding 3914.280s 31946.853us 20 20 100.00
chip_csr_hw_reset 406.150s 6756.764us 5 5 100.00
chip_csr_rw 639.380s 5615.195us 20 20 100.00
xbar_base_random_sequence 100 100 100.00
xbar_random 89.660s 2706.268us 100 100 100.00
xbar_random_delay 600 600 100.00
xbar_smoke_zero_delays 8.280s 53.904us 100 100 100.00
xbar_smoke_large_delays 106.790s 9091.764us 100 100 100.00
xbar_smoke_slow_rsp 103.300s 6520.654us 100 100 100.00
xbar_random_zero_delays 57.120s 623.332us 100 100 100.00
xbar_random_large_delays 488.220s 58098.563us 100 100 100.00
xbar_random_slow_rsp 430.840s 35820.798us 100 100 100.00
xbar_unmapped_address 200 200 100.00
xbar_unmapped_addr 53.420s 1366.891us 100 100 100.00
xbar_error_and_unmapped_addr 57.700s 1324.267us 100 100 100.00
xbar_error_cases 200 200 100.00
xbar_error_random 93.990s 2472.451us 100 100 100.00
xbar_error_and_unmapped_addr 57.700s 1324.267us 100 100 100.00
xbar_all_access_same_device 200 200 100.00
xbar_access_same_device 158.010s 3935.202us 100 100 100.00
xbar_access_same_device_slow_rsp 1133.900s 89129.699us 100 100 100.00
xbar_all_hosts_use_same_source_id 100 100 100.00
xbar_same_source 75.090s 2561.017us 100 100 100.00
xbar_stress_all 200 200 100.00
xbar_stress_all 617.300s 23477.059us 100 100 100.00
xbar_stress_all_with_error 532.260s 16466.909us 100 100 100.00
xbar_stress_with_reset 200 200 100.00
xbar_stress_all_with_rand_reset 738.340s 6497.944us 100 100 100.00
xbar_stress_all_with_reset_error 924.270s 26477.376us 100 100 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 3779.970s 14628.145us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 3093.470s 27753.341us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 4053.980s 22781.473us 3 3 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2951.860s 11571.806us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3670.550s 15420.466us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3778.930s 15543.747us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3704.860s 15525.979us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3329.520s 15704.879us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2796.870s 11905.102us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3501.160s 15892.666us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3894.640s 15954.310us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 4163.100s 15600.008us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 3535.130s 14974.900us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 5206.810s 17731.074us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 6531.590s 24897.369us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 6422.560s 24653.888us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 6717.770s 27324.622us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 6167.080s 23603.142us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 4998.860s 17769.130us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 6858.870s 23850.126us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 6641.320s 24410.630us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 6156.250s 24491.875us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 6543.360s 24061.237us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2528.690s 11157.667us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3581.140s 14916.127us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3357.350s 14396.016us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3500.280s 16866.826us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3351.190s 15497.327us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2690.260s 11929.041us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3690.540s 15149.524us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3510.050s 15248.901us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3380.380s 16361.416us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3348.620s 13795.168us 1 1 100.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 2941.430s 10836.339us 3 3 100.00
rom_e2e_asm_init_dev 4160.640s 16774.619us 3 3 100.00
rom_e2e_asm_init_prod 4130.850s 16775.867us 3 3 100.00
rom_e2e_asm_init_prod_end 3800.080s 16123.459us 3 3 100.00
rom_e2e_asm_init_rma 3833.630s 16360.864us 3 3 100.00
rom_e2e_keymgr_init 7 9 77.78
rom_e2e_keymgr_init_rom_ext_meas 7610.440s 30390.561us 3 3 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 8192.330s 30312.954us 2 3 66.67
rom_e2e_keymgr_init_rom_ext_invalid_meas 7514.440s 29896.837us 2 3 66.67
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 4124.880s 16271.133us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0.000s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0.000s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 245.740s 3234.849us 3 3 100.00
chip_sw_aes_enc_jitter_en 246.660s 3261.449us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 236.430s 3471.032us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 226.990s 3856.331us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_sideload_aes 2066.270s 13053.065us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 277.760s 2910.383us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 469.920s 4790.290us 3 3 100.00
chip_sw_all_escalation_resets 90 100 90.00
chip_sw_all_escalation_resets 632.010s 5485.341us 90 100 90.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 762.110s 5911.306us 3 3 100.00
chip_plic_all_irqs_10 346.540s 3425.273us 3 3 100.00
chip_plic_all_irqs_20 504.620s 4705.194us 3 3 100.00
chip_sw_alert_handler_entropy 3 3 100.00
chip_sw_alert_handler_entropy 259.310s 3733.569us 3 3 100.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 1790.310s 14982.340us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 344.170s 5365.472us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 276.470s 2836.250us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1432.610s 9084.887us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1122.560s 6634.781us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1051.300s 8395.397us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 11560.370s 255074.115us 3 3 100.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 353.340s 3595.736us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 453.160s 6923.223us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 353.340s 3595.736us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1 3 33.33
chip_sw_aon_timer_wdog_bite_reset 684.240s 7323.216us 1 3 33.33
chip_sw_aon_timer_sleep_wdog_bite_reset 1 3 33.33
chip_sw_aon_timer_wdog_bite_reset 684.240s 7323.216us 1 3 33.33
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 498.440s 8258.232us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 534.870s 5919.547us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 774.650s 6261.923us 3 3 100.00
chip_sw_aes_idle 226.990s 3856.331us 3 3 100.00
chip_sw_hmac_enc_idle 248.540s 3688.536us 3 3 100.00
chip_sw_kmac_idle 194.590s 3254.488us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 339.420s 3462.567us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 407.450s 5313.122us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 326.020s 4544.437us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 372.270s 4678.968us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1330.300s 13325.253us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 500.500s 4054.623us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 505.940s 5356.620us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 539.090s 3801.800us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 511.060s 4914.773us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 559.520s 4061.665us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 513.820s 5579.302us 3 3 100.00
chip_sw_ast_clk_outputs 832.230s 7986.263us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 364.850s 7594.510us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 539.090s 3801.800us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 511.060s 4914.773us 3 3 100.00
chip_sw_clkmgr_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 496.120s 4613.648us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 849.500s 6143.121us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4475.290s 20777.435us 3 3 100.00
chip_sw_aes_enc_jitter_en 246.660s 3261.449us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1044.900s 7049.247us 3 3 100.00
chip_sw_hmac_enc_jitter_en 234.160s 3159.549us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1662.240s 12264.526us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 275.330s 3570.190us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 545.750s 5372.152us 3 3 100.00
chip_sw_clkmgr_jitter 197.680s 3159.240us 3 3 100.00
chip_sw_clkmgr_extended_range 33 33 100.00
chip_sw_clkmgr_jitter_reduced_freq 193.870s 3317.714us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 536.740s 5508.447us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 820.390s 8202.706us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4914.160s 24803.090us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 238.370s 3612.018us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 219.430s 3242.532us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1651.190s 12754.634us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 275.200s 3644.316us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 580.630s 6495.635us 3 3 100.00
chip_sw_flash_init_reduced_freq 1514.990s 25364.064us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 19016.820s 129915.227us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 832.230s 7986.263us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 3 3 100.00
chip_sw_clkmgr_sleep_frequency 490.860s 4248.861us 3 3 100.00
chip_sw_clkmgr_reset_frequency 3 3 100.00
chip_sw_clkmgr_reset_frequency 375.710s 3383.109us 3 3 100.00
chip_sw_clkmgr_escalation_reset 90 100 90.00
chip_sw_all_escalation_resets 632.010s 5485.341us 90 100 90.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1432.610s 9084.887us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 1131.290s 6780.230us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 3 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 261.250s 2905.765us 0 3 0.00
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 604.470s 7292.767us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 305.030s 3265.484us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 8102.160s 31481.886us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 199.580s 3011.083us 3 3 100.00
chip_sw_edn_entropy_reqs 1077.370s 7267.821us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 199.580s 3011.083us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 1131.290s 6780.230us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 237.660s 3467.241us 3 3 100.00
chip_sw_flash_init 3 3 100.00
chip_sw_flash_init 1457.080s 20716.554us 3 3 100.00
chip_sw_flash_host_access 6 6 100.00
chip_sw_flash_ctrl_access 747.340s 5938.229us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 849.500s 6143.121us 3 3 100.00
chip_sw_flash_ctrl_ops 6 6 100.00
chip_sw_flash_ctrl_ops 485.630s 4107.324us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en 496.120s 4613.648us 3 3 100.00
chip_sw_flash_rma_unlocked 3 3 100.00
chip_sw_flash_rma_unlocked 4734.120s 43883.954us 3 3 100.00
chip_sw_flash_scramble 3 3 100.00
chip_sw_flash_init 1457.080s 20716.554us 3 3 100.00
chip_sw_flash_idle_low_power 3 3 100.00
chip_sw_flash_ctrl_idle_low_power 294.200s 3861.754us 3 3 100.00
chip_sw_flash_keymgr_seeds 3 3 100.00
chip_sw_keymgr_key_derivation 1437.500s 9453.883us 3 3 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 235.710s 3138.892us 0 3 0.00
chip_sw_flash_creator_seed_wipe_on_rma 3 3 100.00
chip_sw_flash_rma_unlocked 4734.120s 43883.954us 3 3 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 235.710s 3138.892us 0 3 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 235.710s 3138.892us 0 3 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 235.710s 3138.892us 0 3 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 235.710s 3138.892us 0 3 0.00
chip_sw_flash_lc_escalate_en 90 100 90.00
chip_sw_all_escalation_resets 632.010s 5485.341us 90 100 90.00
chip_sw_flash_prim_tl_access 3 3 100.00
chip_prim_tl_access 470.670s 12671.834us 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 685.310s 5407.814us 3 3 100.00
chip_sw_flash_ctrl_escalation_reset 3 3 100.00
chip_sw_flash_crash_alert 575.010s 4816.664us 3 3 100.00
chip_sw_flash_ctrl_write_clear 3 3 100.00
chip_sw_flash_crash_alert 575.010s 4816.664us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 241.970s 2787.887us 3 3 100.00
chip_sw_hmac_enc_jitter_en 234.160s 3159.549us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 248.540s 3688.536us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 2116.180s 11558.960us 3 3 100.00
chip_sw_hmac_multistream_mode 3 3 100.00
chip_sw_hmac_multistream 943.610s 6331.113us 3 3 100.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 485.690s 4978.005us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 462.400s 3852.606us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 631.110s 5356.079us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 405.700s 4502.126us 3 3 100.00
chip_sw_keymgr_key_derivation 6 6 100.00
chip_sw_keymgr_key_derivation 1437.500s 9453.883us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1662.240s 12264.526us 3 3 100.00
chip_sw_keymgr_sideload_kmac 3 3 100.00
chip_sw_keymgr_sideload_kmac 1957.310s 12032.595us 3 3 100.00
chip_sw_keymgr_sideload_aes 3 3 100.00
chip_sw_keymgr_sideload_aes 2066.270s 13053.065us 3 3 100.00
chip_sw_keymgr_sideload_otbn 3 3 100.00
chip_sw_keymgr_sideload_otbn 3192.230s 13576.772us 3 3 100.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 253.240s 3126.509us 3 3 100.00
chip_sw_kmac_mode_kmac 292.620s 3331.779us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 275.330s 3570.190us 3 3 100.00
chip_sw_kmac_app_keymgr 3 3 100.00
chip_sw_keymgr_key_derivation 1437.500s 9453.883us 3 3 100.00
chip_sw_kmac_app_lc 15 15 100.00
chip_sw_lc_ctrl_transition 933.790s 13806.298us 15 15 100.00
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 195.470s 3081.452us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 1648.130s 10078.075us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 194.590s 3254.488us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 469.920s 4790.290us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1187.860s 14704.932us 5 5 100.00
chip_tap_straps_rma 572.630s 9171.418us 5 5 100.00
chip_tap_straps_prod 1728.410s 17770.146us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 201.540s 2839.086us 3 3 100.00
chip_sw_lc_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 933.790s 13806.298us 15 15 100.00
chip_sw_lc_ctrl_transitions 15 15 100.00
chip_sw_lc_ctrl_transition 933.790s 13806.298us 15 15 100.00
chip_sw_lc_ctrl_kmac_req 15 15 100.00
chip_sw_lc_ctrl_transition 933.790s 13806.298us 15 15 100.00
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_key_derivation_prod 2188.890s 12642.922us 3 3 100.00
chip_sw_lc_ctrl_broadcast 76 84 90.48
chip_sw_flash_ctrl_lc_rw_en 235.710s 3138.892us 0 3 0.00
chip_sw_flash_rma_unlocked 4734.120s 43883.954us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 288.270s 3766.823us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 654.660s 7312.179us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 712.530s 6658.606us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 675.400s 7799.739us 0 3 0.00
chip_sw_lc_ctrl_transition 933.790s 13806.298us 15 15 100.00
chip_sw_keymgr_key_derivation 1437.500s 9453.883us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 480.910s 9348.568us 3 3 100.00
chip_sw_sram_ctrl_execution_main 727.910s 7574.651us 3 3 100.00
chip_prim_tl_access 470.670s 12671.834us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 364.850s 7594.510us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 500.500s 4054.623us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 505.940s 5356.620us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 539.090s 3801.800us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 511.060s 4914.773us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 559.520s 4061.665us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 513.820s 5579.302us 3 3 100.00
chip_tap_straps_dev 1187.860s 14704.932us 5 5 100.00
chip_tap_straps_rma 572.630s 9171.418us 5 5 100.00
chip_tap_straps_prod 1728.410s 17770.146us 5 5 100.00
chip_rv_dm_lc_disabled 660.030s 15397.200us 1 3 33.33
chip_lc_scrap 6 6 100.00
chip_sw_lc_ctrl_rma_to_scrap 188.870s 3787.870us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 127.020s 2880.546us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 139.170s 2995.823us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 174.790s 3733.724us 3 3 100.00
chip_lc_test_locked 4 6 66.67
chip_sw_lc_walkthrough_testunlocks 2365.850s 28797.309us 3 3 100.00
chip_rv_dm_lc_disabled 660.030s 15397.200us 1 3 33.33
chip_sw_lc_walkthrough 6 15 40.00
chip_sw_lc_walkthrough_dev 888.810s 12374.360us 0 3 0.00
chip_sw_lc_walkthrough_prod 915.930s 8114.937us 0 3 0.00
chip_sw_lc_walkthrough_prodend 851.320s 10585.181us 3 3 100.00
chip_sw_lc_walkthrough_rma 467.680s 7471.766us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 2365.850s 28797.309us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 9 9 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 99.860s 2503.839us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 102.120s 2328.500us 3 3 100.00
rom_volatile_raw_unlock 72.580s 2475.422us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 4595.830s 17423.868us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4475.290s 20777.435us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 774.650s 6261.923us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 774.650s 6261.923us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 774.650s 6261.923us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 402.690s 4013.997us 3 3 100.00
chip_otp_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 933.790s 13806.298us 15 15 100.00
chip_sw_otp_ctrl_keys 15 15 100.00
chip_sw_flash_init 1457.080s 20716.554us 3 3 100.00
chip_sw_otbn_mem_scramble 402.690s 4013.997us 3 3 100.00
chip_sw_keymgr_key_derivation 1437.500s 9453.883us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 448.340s 5009.734us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 199.770s 2677.385us 3 3 100.00
chip_sw_otp_ctrl_entropy 15 15 100.00
chip_sw_flash_init 1457.080s 20716.554us 3 3 100.00
chip_sw_otbn_mem_scramble 402.690s 4013.997us 3 3 100.00
chip_sw_keymgr_key_derivation 1437.500s 9453.883us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 448.340s 5009.734us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 199.770s 2677.385us 3 3 100.00
chip_sw_otp_ctrl_program 15 15 100.00
chip_sw_lc_ctrl_transition 933.790s 13806.298us 15 15 100.00
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 434.580s 5151.566us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 201.540s 2839.086us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 27 30 90.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 288.270s 3766.823us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 654.660s 7312.179us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 712.530s 6658.606us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 675.400s 7799.739us 0 3 0.00
chip_sw_lc_ctrl_transition 933.790s 13806.298us 15 15 100.00
chip_prim_tl_access 470.670s 12671.834us 3 3 100.00
chip_sw_otp_prim_tl_access 3 3 100.00
chip_prim_tl_access 470.670s 12671.834us 3 3 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1054.020s 7607.046us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 510.960s 8730.120us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1519.390s 28009.452us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 425.320s 7165.320us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 2 3 66.67
chip_sw_pwrmgr_deep_sleep_por_reset 569.610s 7900.509us 2 3 66.67
chip_sw_pwrmgr_normal_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 552.030s 6185.107us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1666.230s 26466.224us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 6 16.67
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 599.850s 10124.900us 0 3 0.00
chip_sw_aon_timer_wdog_bite_reset 684.240s 7323.216us 1 3 33.33
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1449.450s 11820.699us 3 3 100.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 471.990s 4471.931us 3 3 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 510.960s 8730.120us 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 445.170s 5379.353us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 3 33.33
chip_sw_pwrmgr_random_sleep_power_glitch_reset 3270.390s 31189.454us 1 3 33.33
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 458.150s 7875.440us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 458.890s 6687.683us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 3 33.33
chip_sw_pwrmgr_random_sleep_all_reset_reqs 2138.780s 24643.557us 1 3 33.33
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 948.220s 7705.421us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1480.270s 11200.376us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2559.170s 27174.879us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 206.100s 3130.607us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 90 100 90.00
chip_sw_all_escalation_resets 632.010s 5485.341us 90 100 90.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 480.910s 9348.568us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 480.910s 9348.568us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 10 12 83.33
chip_sw_pwrmgr_all_reset_reqs 1480.270s 11200.376us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 2138.780s 24643.557us 1 3 33.33
chip_sw_pwrmgr_wdog_reset 471.990s 4471.931us 3 3 100.00
chip_sw_pwrmgr_smoketest 453.160s 6923.223us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 307.670s 4234.380us 3 3 100.00
chip_sw_rstmgr_cpu_info 0 3 0.00
chip_sw_rstmgr_cpu_info 407.430s 4753.350us 0 3 0.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 388.910s 5168.479us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 1790.310s 14982.340us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 223.540s 3441.752us 3 3 100.00
chip_sw_rstmgr_escalation_reset 90 100 90.00
chip_sw_all_escalation_resets 632.010s 5485.341us 90 100 90.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1122.560s 6634.781us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 638.840s 5148.272us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 710.470s 4892.698us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 269.400s 2982.949us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 199.770s 2677.385us 3 3 100.00
chip_sw_rv_core_ibex_fault_dump 0 3 0.00
chip_sw_rstmgr_cpu_info 407.430s 4753.350us 0 3 0.00
chip_sw_rv_core_ibex_double_fault 0 3 0.00
chip_sw_rstmgr_cpu_info 407.430s 4753.350us 0 3 0.00
chip_jtag_csr_rw 3 3 100.00
chip_jtag_csr_rw 1130.030s 13424.746us 3 3 100.00
chip_jtag_mem_access 3 3 100.00
chip_jtag_mem_access 1126.660s 14176.440us 3 3 100.00
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 307.670s 4234.380us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 239.460s 3121.015us 0 3 0.00
chip_rv_dm_access_after_wakeup 3 3 100.00
chip_sw_rv_dm_access_after_wakeup 422.220s 6503.624us 3 3 100.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 572.630s 9171.418us 5 5 100.00
chip_rv_dm_lc_disabled 1 3 33.33
chip_rv_dm_lc_disabled 660.030s 15397.200us 1 3 33.33
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 762.110s 5911.306us 3 3 100.00
chip_plic_all_irqs_10 346.540s 3425.273us 3 3 100.00
chip_plic_all_irqs_20 504.620s 4705.194us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 232.110s 2482.466us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 211.510s 2590.042us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 3779.970s 14628.145us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 568.130s 7017.157us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 369.610s 4247.084us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 236.060s 3281.168us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 223.760s 2892.021us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 448.340s 5009.734us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 545.750s 5372.152us 3 3 100.00
chip_sw_sleep_sram_ret_contents 6 6 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 545.940s 7193.870us 3 3 100.00
chip_sw_sleep_sram_ret_contents_scramble 575.160s 8240.621us 3 3 100.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 727.910s 7574.651us 3 3 100.00
chip_sw_sram_lc_escalation 96 106 90.57
chip_sw_all_escalation_resets 632.010s 5485.341us 90 100 90.00
chip_sw_data_integrity_escalation 599.980s 6682.741us 6 6 100.00
chip_sw_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 948.220s 7705.421us 3 3 100.00
chip_sw_sysrst_ctrl_reset 1660.690s 24821.380us 3 3 100.00
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 207.670s 3116.099us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 374.070s 4205.645us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 501.980s 4782.875us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 3 3 100.00
chip_sw_sysrst_ctrl_reset 1660.690s 24821.380us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_reset 3 3 100.00
chip_sw_sysrst_ctrl_reset 1660.690s 24821.380us 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2981.980s 20043.566us 3 3 100.00
chip_sw_sysrst_ctrl_flash_wp_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2981.980s 20043.566us 3 3 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 365.760s 5737.973us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0.000s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 223.130s 3232.823us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 231.780s 3570.990us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 427.030s 4544.047us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 342.720s 3348.251us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1320.560s 7624.310us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6235.440s 31974.040us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2356.290s 12356.623us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 201.020s 2936.776us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 249.920s 3249.176us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 3 0.00
chip_sw_rv_core_ibex_lockstep_glitch 171.460s 2912.049us 0 3 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 16063.880s 72479.610us 1 1 100.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 1375.570s 6386.969us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 247.020s 3748.298us 0 1 0.00
rom_e2e_jtag_debug_dev 539.880s 6177.464us 0 1 0.00
rom_e2e_jtag_debug_rma 204.200s 4014.347us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 95.860s 2354.047us 0 1 0.00
rom_e2e_jtag_inject_dev 93.040s 2296.320us 0 1 0.00
rom_e2e_jtag_inject_rma 73.580s 2463.994us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 101.913s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 3 0.00
chip_sw_clkmgr_jitter_frequency 367.950s 4232.518us 0 3 0.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 368.430s 2984.246us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 959.810s 6301.142us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 1471.560s 8608.736us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 306.110s 2864.749us 3 3 100.00
chip_sw_flash_memory_protection 3 3 100.00
chip_sw_flash_ctrl_mem_protection 843.330s 5443.156us 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 164.740s 2839.482us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 237.980s 3373.976us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 3 3 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 413.790s 6351.715us 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 382.200s 4416.963us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1480.270s 11200.376us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 247.020s 3748.298us 0 1 0.00
rom_e2e_jtag_debug_dev 539.880s 6177.464us 0 1 0.00
rom_e2e_jtag_debug_rma 204.200s 4014.347us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 3 3 100.00
chip_sw_rv_dm_access_after_escalation_reset 473.230s 6441.085us 3 3 100.00
chip_sw_plic_alerts 90 100 90.00
chip_sw_all_escalation_resets 632.010s 5485.341us 90 100 90.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 0.000s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 0.000s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 3 3 100.00
chip_sw_spi_device_pinmux_sleep_retention 236.820s 3393.058us 3 3 100.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 533.090s 5024.672us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 4092.640s 18900.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 17 25 68.00
chip_sival_flash_info_access 290.420s 3774.683us 3 3 100.00
chip_sw_rstmgr_rst_cnsty_escalation 545.490s 4971.145us 3 3 100.00
chip_sw_otp_ctrl_rot_auth_config 8.340s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 214.300s 3403.687us 3 3 100.00
chip_sw_otp_ctrl_descrambling 253.650s 2988.937us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 302.390s 4057.616us 2 3 66.67
chip_sw_pwrmgr_sleep_wake_5_bug 13.216s 0.000us 0 3 0.00
chip_sw_flash_ctrl_write_clear 269.830s 3494.353us 3 3 100.00
ate_bootstrap_disjoint 0.000s 0.000us 0 3 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 113543433955050417304828520448774700333410190244979780945543739919199662633348 451
UVM_INFO @ 3421.554000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_mio_dio_val 16345647812983830181099106816402326000892614369250700853496371716130416069498 451
UVM_INFO @ 3458.952000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 6768916794234061400155471213719357668686938176723639934604802597507536108513 320
UVM_INFO @ 4247.084370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 45866307163638173507509550031598649327733782514328446154464017461395276147870 320
UVM_INFO @ 3343.544185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 35289057124947623755571320228776654581574600008753771534064362643453336917066 320
UVM_INFO @ 3869.561474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 70380795367918915436631658433979360133965443470279298250111267618232414838044 309
UVM_INFO @ 3138.891875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_flash_ctrl_lc_rw_en 104258120508531449506336654808347913824350155415224235726948305780790887858127 309
UVM_INFO @ 3001.132856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_flash_ctrl_lc_rw_en 6825090687441359690558699980127076642909793402874986778294616684057304521114 309
UVM_INFO @ 2816.243524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 29857523943472999758236067137687127166778673742597106398787076649349999913072 342
UVM_INFO @ 7799.739145 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 40547661556573238150776657591836059392709915303407466842072921278212916091879 342
UVM_INFO @ 5574.859054 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 85856388209339212204439491688204006705552830473029100891965348161180146614595 347
UVM_INFO @ 6306.900669 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 83947268155393610848295110524696283145063184016097110931175077169717541473140 316
UVM_ERROR @ 3373.976226 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3373.976226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 42437152664339006241012234137312038882488388616341199600672449289303621922681 312
UVM_ERROR @ 3142.756824 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3142.756824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 62529048529581448153797564561044035486221116361684736417935315262804969891928 312
UVM_ERROR @ 2905.764660 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2905.764660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 42646560005367974155923939667900808439227768930158054802453447191095996378623 312
UVM_ERROR @ 3393.940202 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3393.940202 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 110796237833565353539232934702276812526315353515776793195716288059766452271308 317
UVM_ERROR @ 3031.723802 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3031.723802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 69495974096363674409966863637410505819198430886171053559065901580927996501445 317
UVM_ERROR @ 3216.326976 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3216.326976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 59319995877003743975479320330799284068590300089477145992818823520604673460036 317
UVM_ERROR @ 3720.563704 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3720.563704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 59901619050587950784111825587191939557956447804535695749121927903160442561791 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 53862572545114072960731263876780290018318112621044510969056734449633567716404 369
UVM_INFO @ 9968.226500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 6727925549263974706334493181365190794702713825740622846127799012521229645367 369
UVM_INFO @ 8114.936576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 111132116658578113322554182761064779906192958236154946223449620475846911259787 341
UVM_INFO @ 7471.766318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 59597353863239776848813966047122996947830180690407778971347436694129262078207 369
UVM_INFO @ 12374.359825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 16434375537171979003072259080122089954204050697326949288324521579876421160681 369
UVM_INFO @ 8039.172968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 12134995654643540791564779006105239576617968923626695332517838557275827565984 341
UVM_INFO @ 5551.143182 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 53337282303314242095485385629371686349057133157358448402647663041709448295970 369
UVM_INFO @ 13002.974840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 19453994234846326936836503506981667829847831587092487698343150410404495249891 369
UVM_INFO @ 12334.865064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 36803645375973606630122508577614911172501710176787725582144557941177616212541 341
UVM_INFO @ 5281.296905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_sw_rstmgr_cpu_info 53352393875631279486132176181334480345556874562625698095059017242643277597965 333
TL item was: req: (cip_tl_seq_item@109039) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 3389.473313 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 53129255647253243202087741779000277353466190038061586409368276487228749969009 217
TL item was: req: (cip_tl_seq_item@33091) { a_addr: 'h104f4 a_data: 'h6fa2fb6b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb a_opcode: 'h4 a_user: 'h1bd65 d_param: 'h0 d_source: 'hb d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1818.721539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 67058202639809883054491364560923077843791549621624401950628107212301865717230 333
TL item was: req: (cip_tl_seq_item@115999) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 4279.134793 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 61357964380605876693007461109571835197509507695676625903865251573139106415204 217
TL item was: req: (cip_tl_seq_item@39993) { a_addr: 'h1058c a_data: 'hcbd38223 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1b a_opcode: 'h4 a_user: 'h1ba47 d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2327.073048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 42771045361117561721640261465744477798815548327608566661404112294958991984351 224
TL item was: req: (cip_tl_seq_item@31521) { a_addr: 'h1034c a_data: 'h245bb59f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h1ba02 d_param: 'h0 d_source: 'h21 d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1872.218190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 95342754475932137121634461343545265966824204240305180363788815958032879005855 333
TL item was: req: (cip_tl_seq_item@114383) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 4753.349540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 16164867130228092049521178924108601266129424747530204574411378890346397301905 217
TL item was: req: (cip_tl_seq_item@36527) { a_addr: 'h10690 a_data: 'h4ce3c061 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h18aef d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2890.695876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 108004370511399085492129245633335020640430784231438662748197010791564168726571 224
TL item was: req: (cip_tl_seq_item@31907) { a_addr: 'h1059c a_data: 'h2d77c375 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf a_opcode: 'h4 a_user: 'h19eab d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2464.507261 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 2880629758070691144938137171126165850900504369320212863130085433348663902501 224
TL item was: req: (cip_tl_seq_item@31719) { a_addr: 'h1075c a_data: 'h673ee8b6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h18dec d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1969.124330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 13355080127235199976643590095485601458394117770717590283570829823722094238594 217
TL item was: req: (cip_tl_seq_item@33019) { a_addr: 'h1058c a_data: 'h5b302e13 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h1ba79 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2806.739925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 5435816213873483629831919645184415278299307119383024316381119814555019073225 217
TL item was: req: (cip_tl_seq_item@32575) { a_addr: 'h105f8 a_data: 'h289cd82 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h1a247 d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2210.287380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 9909732014574392661021896840739039460986239422168839097873647891775257712727 242
TL item was: req: (cip_tl_seq_item@215087) { a_addr: 'h10350 a_data: 'ha5c0953c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h1869c d_param: 'h0 d_source: 'h17 d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 6780.405590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 68174328400103129803808833539728839373071909217857146271222616061602576341255 242
TL item was: req: (cip_tl_seq_item@214699) { a_addr: 'h105c8 a_data: 'hf34f5b65 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h4 a_user: 'h19e58 d_param: 'h0 d_source: 'h34 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 5342.744137 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 87879096617057151799448533529105015201571148061098904937521817902562129710428 217
TL item was: req: (cip_tl_seq_item@32891) { a_addr: 'h10490 a_data: 'h5c2a528 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc a_opcode: 'h4 a_user: 'h181f7 d_param: 'h0 d_source: 'hc d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2049.644850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 40820534516184693127270896625303750994465426607592625683418831597009823456180 217
TL item was: req: (cip_tl_seq_item@32187) { a_addr: 'h1045c a_data: 'hd89814bf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h181d7 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2642.749150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 39279781656328220274557445669923874483137406935409192653093217310311443461320 224
TL item was: req: (cip_tl_seq_item@31755) { a_addr: 'h104d0 a_data: 'h54e14fb5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h1a96f d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2567.270482 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 74695932362141216276981232063143027982710830741117367208668411985455952121569 217
TL item was: req: (cip_tl_seq_item@32627) { a_addr: 'h1061c a_data: 'haabcfd87 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h1a237 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2575.961323 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 50915098189995630423184997612319847221740764638833390726539750222589194294877 224
TL item was: req: (cip_tl_seq_item@32181) { a_addr: 'h105ac a_data: 'ha7adc99d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h1a2d3 d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2516.067432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 27949475333665423165740009585629314292124400439331717256432675910423403899707 217
TL item was: req: (cip_tl_seq_item@34287) { a_addr: 'h10100 a_data: 'hddf99247 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h18191 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2349.958310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 35769325897137551043592197973366739753429344591391839237392884839512118170274 224
TL item was: req: (cip_tl_seq_item@32087) { a_addr: 'h10560 a_data: 'hc097e68e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1b a_opcode: 'h4 a_user: 'h1a2ca d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2926.513594 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 102063347162273325256742069482181161095431617110842187630744735241586870764623 218
TL item was: req: (cip_tl_seq_item@44555) { a_addr: 'h10558 a_data: 'h7ad3bb6f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h18a0d d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2116.960908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 7593781600966311515490982910988123596856823365422193905676602303129627127718 242
TL item was: req: (cip_tl_seq_item@211209) { a_addr: 'h107c4 a_data: 'h7090eade a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h18d3d d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 5951.321398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 101825819474672507520989002819356105777432067501722134819051933366870950043135 217
TL item was: req: (cip_tl_seq_item@32189) { a_addr: 'h10680 a_data: 'h3b9b0b4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h1ae10 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2423.595511 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 18053003232710059149682736013932064120469279267823477363009087944134146381584 224
TL item was: req: (cip_tl_seq_item@31917) { a_addr: 'h10600 a_data: 'h8544eaac a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1f a_opcode: 'h4 a_user: 'h19ec5 d_param: 'h0 d_source: 'h1f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2133.570306 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 78586535962565003155022860734057372755678911819327721120808884701292476436410 217
TL item was: req: (cip_tl_seq_item@33127) { a_addr: 'h10350 a_data: 'h59315c3b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h186e7 d_param: 'h0 d_source: 'h1e d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2401.615540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 9851782542742474670320831031664232120157526678765893348924410668278166220347 217
TL item was: req: (cip_tl_seq_item@35223) { a_addr: 'h1066c a_data: 'ha980df5f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h1b682 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2214.301580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 107334179502736367066061937365424144252547519780860231461672746018179897144984 218
TL item was: req: (cip_tl_seq_item@101189) { a_addr: 'h104ec a_data: 'h45e3b5a4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h18d3b d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3234.348116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 27108973760711984020472121225850876726891069021124397611969129016868997249326 218
TL item was: req: (cip_tl_seq_item@189299) { a_addr: 'h104a4 a_data: 'h57f9cc77 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h19 a_opcode: 'h4 a_user: 'h1b178 d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3735.440474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 67643012832623750109124893408647003822107969378578366042415921898263316537504 224
TL item was: req: (cip_tl_seq_item@31935) { a_addr: 'h104a8 a_data: 'h17a25212 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h1a904 d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2564.954953 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 52601892576546129812150521457355270332145320635397241639084170829240123691512 217
TL item was: req: (cip_tl_seq_item@33737) { a_addr: 'h10514 a_data: 'hcccae7d6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1bae3 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2108.760094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 111942767226577122580633620201123075445826333107338187300981088260334252517666 224
TL item was: req: (cip_tl_seq_item@31521) { a_addr: 'h104e4 a_data: 'h9a98672d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h199a5 d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2287.902932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 44624760841094011294412450259359305606287599254311536227041991376725275918302 217
TL item was: req: (cip_tl_seq_item@31671) { a_addr: 'h10714 a_data: 'hb3b5634f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h4 a_user: 'h1b1f1 d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2399.167034 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 105358512857226654371465714017882152788735320940649374672163390290012603366806 217
TL item was: req: (cip_tl_seq_item@36203) { a_addr: 'h10588 a_data: 'h7923ede9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h1b689 d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2135.400472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 76915397576510624009724725636318783516787736203595426920337305806779968889287 217
TL item was: req: (cip_tl_seq_item@35697) { a_addr: 'h10374 a_data: 'he29f73e4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h192d3 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2658.305224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 82308486314233744273793796302595156478435209847743488874695120751556720911692 217
TL item was: req: (cip_tl_seq_item@37251) { a_addr: 'h1049c a_data: 'hadfa466d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h199f1 d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2098.579990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 16304899864088433683757004770882838337216230858523276363904081000438400254399 218
TL item was: req: (cip_tl_seq_item@94993) { a_addr: 'h1035c a_data: 'h2da33475 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h19eb1 d_param: 'h0 d_source: 'h2 d_data: 'h100073 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd04 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2640.843692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 82116314166447786120720819812472837835646820231748036844532266272348318013608 217
TL item was: req: (cip_tl_seq_item@32851) { a_addr: 'h10708 a_data: 'hfd047d7f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h18d71 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2701.309935 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 54308554715460984201454294130940025644936646246673863503664411801131226778642 217
TL item was: req: (cip_tl_seq_item@34095) { a_addr: 'h10558 a_data: 'hef29af07 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h18a2e d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2431.601302 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 33399762766321486901399845588908916898474412876043295909305954053591519825835 217
TL item was: req: (cip_tl_seq_item@43251) { a_addr: 'h107e8 a_data: 'hf28a2f76 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h18d99 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2214.798407 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 11527042212334400375676398694967235619264918464924406289505531539014498556680 315
UVM_ERROR @ 5319.660000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5319.660000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 56952526480684282155291456870215735597249160485710721328936232675266964186874 327
UVM_ERROR @ 10124.900000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10124.900000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 11154904386420099606855780993981354006067585825534942369308248619065840239641 435
UVM_ERROR @ 29460.312500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 29460.312500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 60746333448548185471959987794731385400610705217299564144952719037534357134434 319
UVM_ERROR @ 7392.117500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7392.117500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 64430422294715018476596711773462807377807318691531500200752819902802305621993 314
UVM_ERROR @ 5189.533000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5189.533000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 38082518894738666661107017177369547595308929344580789316935855077728034492873 325
UVM_ERROR @ 7424.006000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7424.006000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 60812183077298170187181657302141456489247717105803712739519913491916195595913 319
UVM_ERROR @ 8776.052000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8776.052000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 59526317120764103850028492654876866334046327095988408442815815283732212329349 314
UVM_ERROR @ 5208.736000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5208.736000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 79170422165050965044587225292268253098672184155872775578946300822155008485797 341
UVM_ERROR @ 13436.900000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13436.900000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_rv_timer_systick_test 85391371012996827369928699156140510156470375467513132283470723729716223713988 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 115196932468807131217553166453961597574575726964658294467145191171290317462665 None
chip_sw_alert_handler_lpg_sleep_mode_pings 102198715830340492313396626398993644497532089701217819443301082220179949941756 None
ate_bootstrap_disjoint 73272683173826375542244203376474253793781299276482137215500233261710771917236 None
chip_sw_rv_timer_systick_test 66520415011834385867097841866465707238117827952014912871187474679102253107559 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 96751958709428946812629480933078755413061887239491293850587459492112594743215 None
chip_sw_alert_handler_lpg_sleep_mode_pings 43912517081055726115040511039532570377063230613668098554028346835406356654567 None
ate_bootstrap_disjoint 53269150088239819636180169253416902335452275636204972834465771718068530034331 None
chip_sw_rv_timer_systick_test 28989833749159202656763812291934553502935952356740517700869085578877194465075 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 47654922734959838767622575111592162971309764023591079916583573474863081124687 None
chip_sw_alert_handler_lpg_sleep_mode_pings 109542145394352096737799472907030066986114144717932147462477983082485567070819 None
ate_bootstrap_disjoint 92417633951746895546236936384055511652200957804866920133315111842030658286145 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!
chip_sw_alert_test 100196995949730642934256019291613621566331050223356456088057410863724206386500 307
UVM_INFO @ 2685.526884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_test 50425685644487404271686918332873804986227996533079074196585427630290889907253 307
UVM_INFO @ 2910.383248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 18578437711148482923903654840517613494379736630396866930383843117631586216464 308
UVM_INFO @ 2444.400252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 32608272920379238882904006729854733499467612505597610270003271393651846469614 308
UVM_INFO @ 3507.360401 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84217131990325982198230595094765676228464121619530818573450313350358577773641 308
UVM_INFO @ 2209.258814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 113978146571502535508718504554051519912570547238633163608880891433407410500154 308
UVM_INFO @ 2284.670742 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85649253319937028532424079298673424161629775202822685316551682234048987226415 308
UVM_INFO @ 2486.356648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 73369602867249388862075595723480963911345858412624738368728053144445764407980 308
UVM_INFO @ 2942.629720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 111087512854715254489785285878811976824691241040630857740577516833985311190448 308
UVM_INFO @ 2973.049080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 65550412222156754648205701598558098444975986324456997820738338271243614984 308
UVM_INFO @ 2333.675953 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16980264165175576609457525605621115812153837455115449131951304554820487607181 308
UVM_INFO @ 2897.632333 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55037950042321724963453552100149470649407110475181408111840573043600203503319 308
UVM_INFO @ 3188.553936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14346864130935237001784808499806928143383294682670616910926199103089510243176 308
UVM_INFO @ 3190.097104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 82516923379257045171436380339662817508989674136406126248785335692943925620623 308
UVM_INFO @ 3428.866751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 26984514175469507210045561981637166605933416075804891296805181712665179643784 308
UVM_INFO @ 3678.915825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16947790684093077241198006300373685220480880352019076511766607848808651867478 308
UVM_INFO @ 3055.846520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97794990300983322753439008471733154525018341214873837653341820281422998093731 308
UVM_INFO @ 2836.250010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101203546175190885365144045922362120546634819512440152578326983652836643875037 308
UVM_INFO @ 2972.484318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6195804103999678633212803062527934833999456618035616659452479975245717300008 308
UVM_INFO @ 3245.134040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 91533564562221342788611390323504459706943873256807946170022102962610396966801 308
UVM_INFO @ 2677.752835 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96077000543205537459774593867647800767502566806279583343282031263115721591009 308
UVM_INFO @ 2730.969275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 32580340394603984994550458836551699390186263774405354476048252342342001015114 308
UVM_INFO @ 3285.527455 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 90960061490858812441876613290365864415684145849861864811010425095941996179311 308
UVM_INFO @ 2585.541960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 95455053497105705046644208357085880731453085664594912735336108814826849278449 308
UVM_INFO @ 2767.700285 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55898615280181482422781331791117655995792006343910268237586655968351817546801 308
UVM_INFO @ 2727.455860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89163691572154457687036178732825102926100574104485127763221872355561047557686 308
UVM_INFO @ 2955.248210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88470255308032795356077691340699720970075714327453820995602759217096079070543 308
UVM_INFO @ 3211.676750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 74410122547531677164913039374619635791272132901961524086973121038210469165056 308
UVM_INFO @ 2868.903448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 82918328530539840300143389645494380220908486138442458031344801806300110860825 308
UVM_INFO @ 3329.743888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28892769288217813342628563752115236373397177456732992276146595590422352882746 308
UVM_INFO @ 3096.537530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35015962339213563505432213374315777478564335190796221150814319777794745190311 308
UVM_INFO @ 3021.421745 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19859500243587232208074284650403789626061288260034952835974325506516088060431 308
UVM_INFO @ 2514.915330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 67183722937419832638579588847264237189024200090671243127176885445261036562565 308
UVM_INFO @ 2860.493832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85456997919970230309730322797925485149043461485757210367720183536018381668729 308
UVM_INFO @ 3348.680480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30193415730091484841101692242838234117459179302224769572846811724688329139819 308
UVM_INFO @ 2603.278534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30886992757675582642864447616454665305266756029747100462792407835592495617112 308
UVM_INFO @ 3503.550624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 2677401165897837058733125670229939478251961474052004146536165585751860530956 308
UVM_INFO @ 2678.077736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 111699514547893933844644733849683297972626566150524457509878884141969444634642 308
UVM_INFO @ 2896.480916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 91921610478701948390638063410134857822632232077929093560166889028713227290189 308
UVM_INFO @ 3282.708061 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 31490695674879365588974607858355718076537661142667881244950693210662768961746 308
UVM_INFO @ 2958.381330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 10465977433756909979813565906764146589483638888385551592997701624781750309100 308
UVM_INFO @ 3377.178370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 67049815281371694000586312874010583279139433981608568285646472788998238187067 308
UVM_INFO @ 3204.852300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59888131902829024069911662075372729892966511744126927625355966577414865437218 308
UVM_INFO @ 2944.867932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42644228202603730663992721398140009417795829203326310725932678629123116624438 308
UVM_INFO @ 2004.254036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 41582125933674178746723128121279063687982346372573983970330062365448599329071 308
UVM_INFO @ 2628.060800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39485174815864030714895204788902614865177863822736191521780650361597395087494 308
UVM_INFO @ 3037.665110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 2574489016008336266891586602985281793035710286030376509818733184667391086792 308
UVM_INFO @ 3530.322600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85919696323871162892792735270440881010272481590027660784497861349019297188317 308
UVM_INFO @ 3465.460972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39879061709625060825997425614391211026143096006591826761280476384653573960485 308
UVM_INFO @ 3115.667624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 9341607631234059576235465567849957759582080105898436614379668190934651424257 308
UVM_INFO @ 2990.438050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107101322460828495456771698362792062298896932067156954704954411222186779372884 308
UVM_INFO @ 3334.168660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 25394815045755251710159057029156306426743337986779116042949797515738838773139 308
UVM_INFO @ 2944.280710 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 90644958742543315380203221214244505789506977726295702316601647625781325019954 308
UVM_INFO @ 2889.167744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49123824634244405819567835061291670035236879130769107641925502646374297461657 308
UVM_INFO @ 3088.712040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102065072202159032430451257335455807613570296202577814074361290602020545379384 308
UVM_INFO @ 2751.806280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55127575392605937837952528453315312925833623026189080648612032453782891929515 308
UVM_INFO @ 2861.506212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48548499950074295459951784265319306213038817909037466191359798204544264690816 308
UVM_INFO @ 2907.813526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107034327876608959044407323617384431869784514995397837913885118037173695794020 308
UVM_INFO @ 2633.990453 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 86575346974909270546908137150501086305715918479873827202862093315232057144771 308
UVM_INFO @ 3039.899601 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 36571987812651099933350019911834769880099910316958078830571208746515160952715 308
UVM_INFO @ 2391.555192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 110217489724593937617132244610460369432516165597965032358154035262038441752916 308
UVM_INFO @ 2880.878391 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42915404957656762825665308387103058549814606361024689396245272740740728546918 308
UVM_INFO @ 3268.629496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 24836419581079354804303896398309214711452147669048831775640262559368942807163 308
UVM_INFO @ 2774.227103 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85733932783603942585855558605041805790006179823093699937462403474557489168322 308
UVM_INFO @ 3368.773672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114359194287549715159909000023116446512768867927501079207272192165770820612620 308
UVM_INFO @ 3187.973422 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 76404995114692818271232848085858514855045425134822338475880028327252059885049 308
UVM_INFO @ 2609.291120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 72765664674177576854365275534206633993127819129598105536407954487463071954986 308
UVM_INFO @ 2897.414836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 82470401459017384190183559185653208927589281341446344358209435838585569306700 308
UVM_INFO @ 2830.689626 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6784876307950984938140850901658028981145338516936028572003105924866414346563 308
UVM_INFO @ 2653.363064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 5477605074438179486327921661397991336788897388039844766673844179003598779245 308
UVM_INFO @ 2448.021978 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47944046325702908669465482596822896975592801672066331358707876590642186661838 308
UVM_INFO @ 2741.277218 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28759268527822879611552191824347423473987832580566138824914578775807096508612 308
UVM_INFO @ 2797.658580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 63977914984163033123372258501080086503645251591590962195506121650175023878395 308
UVM_INFO @ 2685.279030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 36817162127453517014439633616874263239338412255069142865101832924565429075618 308
UVM_INFO @ 2798.976830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 36048170668786734546285317952431712742291989457643902102422444511183789166954 308
UVM_INFO @ 2415.743926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 50620493125055306044201183259329974067894846203246677667602100949835355673191 308
UVM_INFO @ 3099.136416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 272844435429813109583822915439590609517144653515775189635820018110328823690 308
UVM_INFO @ 3579.342378 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 92620076435888226086279387669452595657320859374763207488795290833315657233347 308
UVM_INFO @ 3582.371835 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 27237084960486435159728731599905082063442079161981178108078072426511187607314 308
UVM_INFO @ 3306.977474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 38992495283737466432852872827680174393816959255208144200115410096005034728748 308
UVM_INFO @ 3012.087048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28782394104661808733586579089365466700154677583495727771379933428753810191947 308
UVM_INFO @ 3456.237607 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 63699517255724263588201832379664043422780438801274402697387446806812714526539 308
UVM_INFO @ 2990.577700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 18636423404858820414736597315187695265604054176134036565953789728885007897643 308
UVM_INFO @ 2872.447612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 21938229277513326361955438999911142572885844364398426587248121366571299982398 308
UVM_INFO @ 2519.614032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 43489902489339673302784054651143225024579588190987664292858643833615072303613 308
UVM_INFO @ 2316.205076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 54026683764120681498963351059142222555477786643188276745439401358467146481922 308
UVM_INFO @ 2175.138854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62847961677451094155943071174139884515180547857662790000156413244931206300767 308
UVM_INFO @ 2672.801400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16198132433060399454013114191114182250243173228365259792418981980882257734070 308
UVM_INFO @ 3102.469864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30515307091675106643630586592822794526992144668106884563591834878506405220416 308
UVM_INFO @ 2586.157304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34776984588126477716897530793055700020424160426928231386123199618716175847200 308
UVM_INFO @ 2925.220290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68564700623822094640585791332574507093438429342600924320578740810653781469339 308
UVM_INFO @ 2813.639778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68629582556614589845762178040739455239841574650842698334256432449167452862317 308
UVM_INFO @ 2927.949882 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 51409370428614243307933665604388340544357785225698985655034307608772673745940 343
UVM_INFO @ 3613.723275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 102764370571713827416500082369987220530748996966972096807094843216414677560068 343
UVM_INFO @ 3725.289856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 9955056783380857137887949833511465739269025004414065384851683657105424598944 343
UVM_INFO @ 4232.517508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 92621991452503389362123286424271588317703247757330252237512676420660538757159 311
UVM_INFO @ 3468.179042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 109008995032933375504798130489820470576591169624442939165015332956889689509871 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 54169548718751617848773858011864086368762829448342033046380184119382709147316 None
Another command (pid=287774) is running. Waiting for it to complete on the server (server_pid=287895)...
Another command (pid=291541) is running. Waiting for it to complete on the server (server_pid=287895)...
Another command (pid=292548) is running. Waiting for it to complete on the server (server_pid=287895)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 50605937622241620977143050170325452573875022877295872543230009979486047615561 None
---- STDERR ----
Another command (pid=3942810) is running. Waiting for it to complete on the server (server_pid=287895)...
Another command (pid=3943477) is running. Waiting for it to complete on the server (server_pid=287895)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 69049219506723056796523761590028922007988781803575677141830191863594266045533 None
Another command (pid=321086) is running. Waiting for it to complete on the server (server_pid=287895)...
Another command (pid=324847) is running. Waiting for it to complete on the server (server_pid=287895)...
Another command (pid=324175) is running. Waiting for it to complete on the server (server_pid=287895)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 3085354004494903079798764604916739286572341183395432890080366170352452498586 None
---- STDERR ----
Another command (pid=697650) is running. Waiting for it to complete on the server (server_pid=287895)...
Another command (pid=699343) is running. Waiting for it to complete on the server (server_pid=287895)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 20295769610559257687243056238117406744516634519012830394791822942141201986805 None
Another command (pid=340945) is running. Waiting for it to complete on the server (server_pid=287895)...
Another command (pid=288884) is running. Waiting for it to complete on the server (server_pid=287895)...
Another command (pid=348739) is running. Waiting for it to complete on the server (server_pid=287895)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 50338385700101834158516199720927734349656035509808119839205431348418809351388 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 89854189261751520452447006818762405950276950955162880577249323952528483315650 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 95738119042551227067765561666018694967210805197138946414189427474900166018043 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 7298899483275373458183841664327979425999996884273383697350365883797577587222 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 23443329472446224867310344257598844668056644419980089056388253775203189677524 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 101111496691698952417053430031544678502173302608732086796265482394162408747246 307
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 100500794254826294984841348011614727848896399363844297131890805241991627919704 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 56052087157820593306600714901569068584629446175192600190170522900867252036803 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 94105701021150753921921449230288093352116424457036032466391174072408826268236 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 84782539584844944865861048715050626605474874101566412473696767170833190046229 322
UVM_INFO @ 1322.448638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_core_ibex_lockstep_glitch 49075030735070715055837620283204588813998548751025385119405997802765186929904 322
UVM_INFO @ 2415.798673 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_core_ibex_lockstep_glitch 70277997935495347853224705324988365577263662820984426721173954160422166822197 331
UVM_INFO @ 2912.049370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 22878760207250712318394509784697662099497696559285271738487112257447196560599 312
UVM_INFO @ 2819.505000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 34172932656101610580418587557968202077795995267591960014791175257619165343696 312
UVM_INFO @ 3389.198500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 76754340492233481079419715488187775386559707889940034012767470620136431875925 317
UVM_INFO @ 3974.046000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 58785136630531313507651184700997259232786340241677874671009594890385364457263 318
UVM_INFO @ 2669.142000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 99595768119650701264101644325249090886734370205627696246465194875717640678779 318
UVM_INFO @ 3369.895000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 84811279788366912099869044796270923039625308638707194825371351222256891695326 323
UVM_INFO @ 2745.770000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 32085580955335069070634580251216277589469991138824339920002236601517373111865 327
UVM_INFO @ 10771.386438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 58458351486146901640651984850703503724932783152351998491320690078427749410195 327
UVM_INFO @ 14310.345614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 107855476491324403694214146622162770361500244457237973590005362669111636622257 327
UVM_INFO @ 10816.379600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 46972931090602624899597190071073861490813140572234233268233173174942458124450 319
UVM_INFO @ 15710.935800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 82904653050956003737451410479951191165868144160832795606405943889729016140845 327
UVM_ERROR @ 4213.452756 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4213.452756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 67078489991309328990134883822413286113193617277632044651051245408447322060038 327
UVM_ERROR @ 5536.549492 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5536.549492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 39794930253965036265128201867397914876434967539905754561837158522714999791418 327
UVM_ERROR @ 4019.209856 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4019.209856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 77163251055231950701283606057498133118756865284634178909132444513855107783816 374
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 12781200082ps failed at 12781200082ps
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 12781283410ps failed at 12781283410ps
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 26949116557073563992719438190244607000627715166652711774754326733039470494809 307
UVM_INFO @ 3629.402760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 103740198082860528330200284882160055516715800337441324670632590291898276808593 215
UVM_INFO @ 2289.292697 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 34361207957855809710585580317044987574980300542941091992321872683353280076578 237
UVM_INFO @ 4724.995275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reset_cause == HwReq)'
chip_sw_sensor_ctrl_alert 102840142114720377243373724349075820759667353177169145358853783199341180852295 316
UVM_ERROR @ 2615.940318 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2615.940318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sensor_ctrl_alert 44117409288259793872691395507885125003757940576600878009323629908935734156822 316
UVM_ERROR @ 3411.793524 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 3411.793524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 42374821952941905407516298576076529555605584614158179775713683602332254393332 319
UVM_INFO @ 20985.185470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
rom_raw_unlock 48125051689461629976106523856143439897061208845013156282701950579282356977842 322
UVM_INFO @ 16537.126905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
chip_sw_all_escalation_resets 115164010683782755551102151634982111934529005458282867441659371106374954196033 316
UVM_INFO @ 2593.495828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 40963125821211262032417267930051785304425576719096870767244233528485872672821 316
UVM_INFO @ 2654.777400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 91393479682904262659021152118089480645226981133178387921430160279138979254935 316
UVM_INFO @ 3489.968088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 39603635459445725642085303962369166742626707232840627763364434163974224748504 316
UVM_INFO @ 3065.312802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *
chip_sw_all_escalation_resets 73857869160099089279709318343785260526565579027537351640191878787927220674603 317
UVM_INFO @ 3149.262448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 50366432522632915397361952381864792175817535866582988740455428086147727529305 317
UVM_INFO @ 3165.154896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 3253545269017583863065206597597527642537944092913325946228144985382295481776 317
UVM_INFO @ 3006.837672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---