Simulation Results: clkmgr

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.90 %
  • code
  • 98.64 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.11 %
  • branch
  • 98.84 %
  • cond
  • 96.06 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.62%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 1.540s 133.833us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 1.190s 39.739us 5 5 100.00
csr_rw 20 20 100.00
clkmgr_csr_rw 1.260s 52.976us 20 20 100.00
csr_bit_bash 5 5 100.00
clkmgr_csr_bit_bash 8.550s 762.546us 5 5 100.00
csr_aliasing 5 5 100.00
clkmgr_csr_aliasing 1.690s 68.576us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.110s 148.279us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
clkmgr_csr_rw 1.260s 52.976us 20 20 100.00
clkmgr_csr_aliasing 1.690s 68.576us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.580s 192.903us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 1.720s 127.566us 50 50 100.00
extclk 50 50 100.00
clkmgr_extclk 1.680s 235.722us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 1.270s 105.406us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 1.540s 133.833us 50 50 100.00
frequency 50 50 100.00
clkmgr_frequency 12.540s 1998.052us 50 50 100.00
frequency_timeout 50 50 100.00
clkmgr_frequency_timeout 9.830s 2423.092us 50 50 100.00
frequency_overflow 50 50 100.00
clkmgr_frequency 12.540s 1998.052us 50 50 100.00
stress_all 50 50 100.00
clkmgr_stress_all 114.280s 12390.297us 50 50 100.00
alert_test 50 50 100.00
clkmgr_alert_test 1.580s 294.726us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 5.260s 619.490us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 5.260s 619.490us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
clkmgr_csr_hw_reset 1.190s 39.739us 5 5 100.00
clkmgr_csr_rw 1.260s 52.976us 20 20 100.00
clkmgr_csr_aliasing 1.690s 68.576us 5 5 100.00
clkmgr_same_csr_outstanding 1.960s 99.405us 20 20 100.00
tl_d_partial_access 50 50 100.00
clkmgr_csr_hw_reset 1.190s 39.739us 5 5 100.00
clkmgr_csr_rw 1.260s 52.976us 20 20 100.00
clkmgr_csr_aliasing 1.690s 68.576us 5 5 100.00
clkmgr_same_csr_outstanding 1.960s 99.405us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 20 25 80.00
clkmgr_sec_cm 1.460s 63.836us 0 5 0.00
clkmgr_tl_intg_err 3.910s 777.305us 20 20 100.00
shadow_reg_update_error 20 20 100.00
clkmgr_shadow_reg_errors 2.750s 269.165us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
clkmgr_shadow_reg_errors 2.750s 269.165us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
clkmgr_shadow_reg_errors 2.750s 269.165us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
clkmgr_shadow_reg_errors 2.750s 269.165us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
clkmgr_shadow_reg_errors_with_csr_rw 5.900s 1411.491us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
clkmgr_tl_intg_err 3.910s 777.305us 20 20 100.00
sec_cm_meas_clk_bkgn_chk 50 50 100.00
clkmgr_frequency 12.540s 1998.052us 50 50 100.00
sec_cm_timeout_clk_bkgn_chk 50 50 100.00
clkmgr_frequency_timeout 9.830s 2423.092us 50 50 100.00
sec_cm_meas_config_shadow 20 20 100.00
clkmgr_shadow_reg_errors 2.750s 269.165us 20 20 100.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 2.060s 253.146us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
clkmgr_lc_ctrl_intersig_mubi 1.590s 406.344us 50 50 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 50 50 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.580s 237.548us 50 50 100.00
sec_cm_clk_handshake_intersig_mubi 49 50 98.00
clkmgr_clk_handshake_intersig_mubi 1.360s 68.077us 49 50 98.00
sec_cm_div_intersig_mubi 50 50 100.00
clkmgr_div_intersig_mubi 1.430s 91.646us 50 50 100.00
sec_cm_jitter_config_mubi 20 20 100.00
clkmgr_csr_rw 1.260s 52.976us 20 20 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 1.460s 63.836us 0 5 0.00
sec_cm_meas_config_regwen 20 20 100.00
clkmgr_csr_rw 1.260s 52.976us 20 20 100.00
sec_cm_clk_ctrl_config_regwen 20 20 100.00
clkmgr_csr_rw 1.260s 52.976us 20 20 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 1.460s 63.836us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 50 50 100.00
clkmgr_regwen 7.580s 1681.562us 50 50 100.00
stress_all_with_rand_reset 50 50 100.00
clkmgr_stress_all_with_rand_reset 122.160s 23045.875us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 96093168549377691587968922627367695233301511974815588323647314121191348510019 79
UVM_INFO @ 5229875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 107121428647303193261289605326603629381158948245875737311810410510815397740641 88
UVM_INFO @ 16393632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 60606492570306710086155594737302121465491735700371786606588432409094073831194 94
UVM_INFO @ 49145290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 36451887234689354480711860168108983175327353158447897167547931148791145155941 114
UVM_INFO @ 108299322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 99935342446324881999931541596140614659816255815476836086287745927919442842067 104
UVM_INFO @ 63836405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch
clkmgr_clk_handshake_intersig_mubi 96144912970333953854815815193524189079234837624296971779024373063680749295482 74
UVM_INFO @ 11648779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---