Simulation Results

Simulation Results: csrng

12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.31 %

code
96.23 %

assert
95.85 %

func
90.86 %

block
98.59 %

line
99.57 %

branch
96.46 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		96.87%
V2S		99.85%
V3		0.00%

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	csrng_smoke	36.000s	96.255us	50	50	100.00
csr_hw_reset				5	5	100.00
	csrng_csr_hw_reset	35.000s	25.360us	5	5	100.00
csr_rw				20	20	100.00
	csrng_csr_rw	35.000s	94.106us	20	20	100.00
csr_bit_bash				5	5	100.00
	csrng_csr_bit_bash	40.000s	191.561us	5	5	100.00
csr_aliasing				5	5	100.00
	csrng_csr_aliasing	42.000s	691.358us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	csrng_csr_mem_rw_with_rand_reset	35.000s	86.063us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	csrng_csr_rw	35.000s	94.106us	20	20	100.00
	csrng_csr_aliasing	42.000s	691.358us	5	5	100.00

1424/1470 passed

96.87 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	43.000s	577.246us	500	500	100.00
err				500	500	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
cmds				6	50	12.00
	csrng_cmds	137.000s	10896.517us	6	50	12.00
life cycle				6	50	12.00
	csrng_cmds	137.000s	10896.517us	6	50	12.00
stress_all				48	50	96.00
	csrng_stress_all	1501.000s	112205.461us	48	50	96.00
intr_test				50	50	100.00
	csrng_intr_test	35.000s	12.027us	50	50	100.00
alert_test				50	50	100.00
	csrng_alert_test	35.000s	19.308us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	csrng_tl_errors	38.000s	109.263us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	csrng_tl_errors	38.000s	109.263us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	csrng_csr_hw_reset	35.000s	25.360us	5	5	100.00
	csrng_csr_rw	35.000s	94.106us	20	20	100.00
	csrng_csr_aliasing	42.000s	691.358us	5	5	100.00
	csrng_same_csr_outstanding	35.000s	29.727us	20	20	100.00
tl_d_partial_access				50	50	100.00
	csrng_csr_hw_reset	35.000s	25.360us	5	5	100.00
	csrng_csr_rw	35.000s	94.106us	20	20	100.00
	csrng_csr_aliasing	42.000s	691.358us	5	5	100.00
	csrng_same_csr_outstanding	35.000s	29.727us	20	20	100.00

V2S

1343/1345 passed

99.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	csrng_sec_cm	37.000s	323.802us	5	5	100.00
	csrng_tl_intg_err	38.000s	327.929us	20	20	100.00
sec_cm_config_regwen				70	70	100.00
	csrng_regwen	35.000s	61.408us	50	50	100.00
	csrng_csr_rw	35.000s	94.106us	20	20	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	43.000s	577.246us	500	500	100.00
sec_cm_intersig_mubi				48	50	96.00
	csrng_stress_all	1501.000s	112205.461us	48	50	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
	csrng_sec_cm	37.000s	323.802us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
	csrng_sec_cm	37.000s	323.802us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
	csrng_sec_cm	37.000s	323.802us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
	csrng_sec_cm	37.000s	323.802us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
	csrng_sec_cm	37.000s	323.802us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	43.000s	577.246us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
sec_cm_constants_lc_gated				48	50	96.00
	csrng_stress_all	1501.000s	112205.461us	48	50	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	43.000s	577.246us	500	500	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	csrng_tl_intg_err	38.000s	327.929us	20	20	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
	csrng_sec_cm	37.000s	323.802us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00
	csrng_sec_cm	37.000s	323.802us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	43.000s	661.930us	200	200	100.00
	csrng_err	35.000s	25.820us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	72.000s	4999.607us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])
	csrng_cmds	40732770785981687267755046325129552876754850355810128143749450008844956337288	130	UVM_INFO @ 24721436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107801874207484123836316194099931090402549042935826240512828666238749218936472	130	UVM_INFO @ 38107875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	105702458189612898642398534278271634944252417782256068085994020159698366982822	130	UVM_INFO @ 83694145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	71965834488976349188377423885745535499408109097202405543436813384073652608286	130	UVM_INFO @ 362882521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	32027894245516371172601808147976365297225135157501116277984612243912079007031	130	UVM_INFO @ 123084575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107625893913165348359575077438875977525937592086535837652798184530940746100833	130	UVM_INFO @ 68653317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	99346940077138739533070222676585813873262045299408578985471627287740565658966	140	UVM_INFO @ 185692457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60280459947129246726373679427172750824434310581226357295799106812614498669591	130	UVM_INFO @ 192788888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	52549212349772628542889914969505844236888946477518849247517209586402642672266	130	UVM_INFO @ 43819454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24768673881249138396402195152143394040542498606159893941016499714726005875289	130	UVM_INFO @ 378484695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	100955475378545642943152017395578100470642773939156390529730030674031271021173	130	UVM_INFO @ 200820788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	85377410723311835430436859550004941863887361163002062037865824976534230558797	130	UVM_INFO @ 106383321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	2988918209699310724787704151517663563186741042213802599206067057580086860249	140	UVM_INFO @ 238349485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	88950534326226190011639651660163417810766402445229064231534558974944142733051	130	UVM_INFO @ 259801500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	115115823481821744485069920563620246433829732122115714830342411747553086679525	130	UVM_INFO @ 210208984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	6684888226319027057478597011185895114086917626414344845732644341919852650424	130	UVM_INFO @ 127929552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	45341600282261894584132059270538997411699130014369476259757842485500555887004	140	UVM_INFO @ 754781027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	65933247316056752887928781457714178396840103028636759629587089403725513249977	130	UVM_INFO @ 27995997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	92720645883481128785780204516007815123715305894909227498879714352614910495862	130	UVM_INFO @ 114559494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	56567926454155308059576764442753427859924456560667775296156520646304488380290	130	UVM_INFO @ 39833790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	16250426623096496567001889918695786101860018624811629013071995888541832265577	130	UVM_INFO @ 181474729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	32083878322829591802315124465076487344918264997498417459070323126222260541655	130	UVM_INFO @ 47057598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	100996093461319292789115788432008014177401026250717746058348996114100286721479	130	UVM_INFO @ 97922830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	80741836893501857245639579332701700252223278539173799127982417299161645865807	130	UVM_INFO @ 90704388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	81184968853677458895628415102390186449120315902162575711816591271078009314708	180	UVM_INFO @ 3833094996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	62763371255148495828748256022340720348641197429146314124272558996342721868700	130	UVM_INFO @ 308141263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	72314449014531320816843565040779344537997590222568939321183728511235466909839	130	UVM_INFO @ 398541302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	20031651659495749369795848668091715263797155241952725110560425574641533768642	130	UVM_INFO @ 113657890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60469100204288874894447394253642794397882767374969068227131679751233420014612	130	UVM_INFO @ 143473084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	82173397290524098100184411339394402044446395756136376093889250707515724067656	130	UVM_INFO @ 42816940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	39244268435678445960717234323031957902350961803706281215490094572370156614588	140	UVM_INFO @ 168597190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114159986271313901336686266758987262634570070135116701797191866652824212088294	130	UVM_INFO @ 120830757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	112829761051131566350720864764460833046614897526773495192715974822250823625149	130	UVM_INFO @ 52604510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	85402749871839894975224108763647235814249386920555691058374772764071189498110	130	UVM_INFO @ 90638649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114680297954722795165661127734534867657551487318707986107176634751192922902608	130	UVM_INFO @ 181321182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46811606884609307976315631532153947425986560690965345499784146080466371561624	130	UVM_INFO @ 394032390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	11379152516823725197399356277626434872501887328483322999811221073918634273698	130	UVM_INFO @ 23844289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	96067474090577631225844919673186581794623988526161396707971862729383979883388	140	UVM_INFO @ 374181748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	14532763205285194607147793897990988335687137803154296645789708046904743718468	130	UVM_INFO @ 104173605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	76604702415469993433442350706790499638197022680277690570129187301497101226284	130	UVM_INFO @ 124430189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job killed!
	csrng_stress_all_with_rand_reset	77553310979925828462575617159297970247679582159672149234209693743773804970486	None
	csrng_stress_all_with_rand_reset	68305501160584127421320517324790028985038351385999609825468079978686651849781	None
	csrng_stress_all_with_rand_reset	70948007805572933735492671479036656481726178105550597157056491012121386548847	None
	csrng_stress_all_with_rand_reset	101110210634892187234301564998515903855678018403251903931547426258595918301579	None
	csrng_stress_all_with_rand_reset	114253381266624530713053280557960718132071339029817005628654281143000141672075	None
	csrng_stress_all_with_rand_reset	66482698968855608330209578069211077505459319626490009482367141979961337998463	None
	csrng_stress_all_with_rand_reset	33011033765475556954945881130087829599443355869299387769857027083594941767663	None
	csrng_stress_all_with_rand_reset	69549827743511219759390638412484152318174431508950106296331809934218904419799	None
	csrng_stress_all_with_rand_reset	75464355300156286739517015877817345706843999399335080792991849361822958571543	None
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])
	csrng_cmds	61811072426873295709177556628272271827025533686653645916656600393323587665829	149	UVM_INFO @ 301881474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	28487772905821485812408979574345044630872820970713423340551692847149601109481	139	UVM_INFO @ 29257625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started
	csrng_stress_all_with_rand_reset	67815903806396883858617497458732053489974214302038319087230597593269361794186	126	UVM_INFO @ 4999606735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:293) [scoreboard] Check failed cmd_sts[SW_APP] == item.d_data[:] (* [] vs [*])
	csrng_cmds	109413943879505701978098557974733498785421426593051361064936016319805993742723	138	UVM_INFO @ 12921288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits
	csrng_cmds	60549875660972975176055732393019536093974649187094061536878550550883977264508	133	UVM_INFO @ 87539902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq
	csrng_stress_all	105359838209290142798420184698482917406149121703949502039511488590503164498656	145	UVM_INFO @ 160029506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	28189733229227326393647404799561774836114271683401463023102494531829786992793	163	UVM_INFO @ 29092601351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---