Simulation Results: edn/edn0

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.39 %
  • code
  • 95.51 %
  • assert
  • 97.61 %
  • func
  • 93.06 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.12 %
  • FSM
  • 90.86 %
Validation stages
V1
100.00%
V2
99.48%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 0.970s 19.526us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.180s 26.636us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.070s 17.030us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.520s 1768.549us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.230s 31.987us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.580s 130.291us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.070s 17.030us 20 20 100.00
edn_csr_aliasing 1.230s 31.987us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 3.860s 656.649us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 3.860s 656.649us 300 300 100.00
genbits 300 300 100.00
edn_genbits 3.860s 656.649us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.180s 21.950us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.180s 27.108us 200 200 100.00
errs 100 100 100.00
edn_err 1.210s 33.513us 100 100 100.00
disable 95 100 95.00
edn_disable 1.070s 38.191us 50 50 100.00
edn_disable_auto_req_mode 7.510s 500.000us 45 50 90.00
stress_all 50 50 100.00
edn_stress_all 9.260s 397.559us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.920s 18.674us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.040s 35.223us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.970s 2114.854us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.970s 2114.854us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.180s 26.636us 5 5 100.00
edn_csr_rw 1.070s 17.030us 20 20 100.00
edn_csr_aliasing 1.230s 31.987us 5 5 100.00
edn_same_csr_outstanding 1.240s 78.201us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.180s 26.636us 5 5 100.00
edn_csr_rw 1.070s 17.030us 20 20 100.00
edn_csr_aliasing 1.230s 31.987us 5 5 100.00
edn_same_csr_outstanding 1.240s 78.201us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 7.230s 673.078us 5 5 100.00
edn_tl_intg_err 4.320s 702.932us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.010s 17.269us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.180s 27.108us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.230s 673.078us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.230s 673.078us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.230s 673.078us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.230s 673.078us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.180s 27.108us 200 200 100.00
edn_sec_cm 7.230s 673.078us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.180s 27.108us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 4.320s 702.932us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 45 50 90.00
edn_stress_all_with_rand_reset 152.430s 15286.916us 45 50 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 25615192836220344853112240116587065894915866533036659077588350145106897557055 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 76849160314014932303876471886457009080271551566372950254682768304114377662986 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 24661690030511405156670738228888134210999585643232212283872670518025425452749 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 24718988433831072113468521817349647031277855810746052761927668615077948912738 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 62887447537060020182751399798669654793894777725493393894167072521898414654001 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 80367778795930648186672284681057684271172022275842347719136614863265061997013 213
UVM_INFO @ 991417234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 111030337687276897240520970125940215862367735959206352265138577901569934348033 115
UVM_INFO @ 505984202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 41316939936277644054798487872795278425926706176836788267378190975774252409346 124
UVM_INFO @ 798015902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 30169841629741479421628862337735439311210506222502252607250049369785477923023 169
UVM_INFO @ 1311497985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 54973679406902982465928438269691766527868810123518927349554039109845552069041 150
UVM_INFO @ 1566886368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---