Simulation Results: edn/edn1

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.10 %
  • code
  • 95.93 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
99.38%
V2S
100.00%
V3
96.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 0.910s 19.469us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.820s 31.130us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.810s 17.196us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.800s 517.004us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.120s 220.494us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.310s 33.197us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.810s 17.196us 20 20 100.00
edn_csr_aliasing 1.120s 220.494us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 93.400s 9088.098us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 93.400s 9088.098us 300 300 100.00
genbits 300 300 100.00
edn_genbits 93.400s 9088.098us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.010s 21.058us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.280s 360.955us 200 200 100.00
errs 100 100 100.00
edn_err 1.140s 35.868us 100 100 100.00
disable 94 100 94.00
edn_disable 0.820s 19.685us 50 50 100.00
edn_disable_auto_req_mode 6.960s 500.000us 44 50 88.00
stress_all 50 50 100.00
edn_stress_all 7.420s 372.569us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.830s 19.460us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 0.880s 25.882us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.030s 581.288us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.030s 581.288us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.820s 31.130us 5 5 100.00
edn_csr_rw 0.810s 17.196us 20 20 100.00
edn_csr_aliasing 1.120s 220.494us 5 5 100.00
edn_same_csr_outstanding 1.120s 41.141us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.820s 31.130us 5 5 100.00
edn_csr_rw 0.810s 17.196us 20 20 100.00
edn_csr_aliasing 1.120s 220.494us 5 5 100.00
edn_same_csr_outstanding 1.120s 41.141us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 4.040s 4103.953us 5 5 100.00
edn_tl_intg_err 8.830s 1978.196us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.860s 31.204us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.280s 360.955us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.040s 4103.953us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.040s 4103.953us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.040s 4103.953us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.040s 4103.953us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.280s 360.955us 200 200 100.00
edn_sec_cm 4.040s 4103.953us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.280s 360.955us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 8.830s 1978.196us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 48 50 96.00
edn_stress_all_with_rand_reset 124.480s 18172.919us 48 50 96.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 37090960711260031569195688625435067655871407428815939227111181025400036210135 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 72111732300515772440671473916467101462966409158790643215255944720637292329899 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 14097359621372097130986995547117412328921933426551651072693780788187636422072 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 65937076539119990370292473105711260177120415933569493794743400608690175242939 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 33162271197359669080575139956460121215334375245629443443314428014655287522616 221
UVM_INFO @ 2715565875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 17948017439122452465743419006828934044984178721804958489923937119228874527138 222
UVM_INFO @ 1755510748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 47335875101481264409503845486022442346258740142564108740581620277333848261949 88
UVM_INFO @ 60285990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 43617921122305901679376545493514794736955618882998465582271754667549722680926 88
UVM_INFO @ 45623268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---