Simulation Results

Simulation Results: flash_ctrl

12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.99 %

code
95.77 %

assert
96.76 %

func
98.45 %

line
96.10 %

branch
97.45 %

cond
94.82 %

toggle
98.66 %

FSM
91.84 %

Validation stages

V1		100.00%
V2		98.66%
V2S		98.56%
V3		100.00%
unmapped		100.00%

120/120 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	160.940s	68.629us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	23.170s	95.526us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	42.050s	863.908us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	18.620s	225.286us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	66.820s	9221.276us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	50.690s	1692.547us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	19.050s	189.108us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	18.620s	225.286us	20	20	100.00
	flash_ctrl_csr_aliasing	50.690s	1692.547us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	12.430s	50.508us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	11.600s	19.526us	5	5	100.00

1029/1043 passed

98.66 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	23.820s	43.167us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	73.050s	234.888us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1715.420s	135770.142us	3	3	100.00
	flash_ctrl_hw_rma_reset	898.180s	210202.163us	20	20	100.00
	flash_ctrl_lcmgr_intg	13.860s	40.734us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	2246.940s	249617.145us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	382.430s	10251.195us	5	5	100.00
program_reset				29	30	96.67
	flash_ctrl_prog_reset	207.920s	8006.205us	29	30	96.67
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	2559.440s	244117.312us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	122.810s	2507.276us	5	5	100.00
rd_buff_eviction_w_ecc				98	100	98.00
	flash_ctrl_rw_evict	32.010s	67.217us	39	40	97.50
	flash_ctrl_rw_evict_all_en	32.470s	31.732us	39	40	97.50
	flash_ctrl_re_evict	33.960s	62.681us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	245.080s	4572.328us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	245.080s	4572.328us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	900.300s	30407.648us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	30.290s	7143.352us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	836.260s	6068.093us	20	20	100.00
error_mp				9	10	90.00
	flash_ctrl_error_mp	617.070s	32364.222us	9	10	90.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	482.610s	4482.957us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1377.430s	850.248us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	13.520s	88.152us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	161.190s	1512.418us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	22.920s	143.610us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	17.240s	32.958us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	717.620s	852.729us	5	5	100.00
secret_partition				130	130	100.00
	flash_ctrl_hw_sec_otp	224.700s	3171.217us	50	50	100.00
	flash_ctrl_otp_reset	135.350s	39.178us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1715.420s	135770.142us	3	3	100.00
interrupts				97	100	97.00
	flash_ctrl_intr_rd	207.660s	28746.689us	39	40	97.50
	flash_ctrl_intr_wr	83.120s	20801.988us	10	10	100.00
	flash_ctrl_intr_rd_slow_flash	398.720s	237306.322us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	369.010s	205940.456us	8	10	80.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	74.060s	1815.514us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	68.060s	3299.733us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	22.590s	26.555us	5	5	100.00
	flash_ctrl_ro_derr	122.150s	1978.800us	10	10	100.00
	flash_ctrl_rw_derr	259.050s	7249.030us	10	10	100.00
	flash_ctrl_derr_detect	185.100s	9442.465us	5	5	100.00
	flash_ctrl_integrity	455.930s	3849.959us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	17.270s	78.126us	5	5	100.00
	flash_ctrl_ro_serr	122.970s	794.855us	10	10	100.00
	flash_ctrl_rw_serr	189.820s	2276.239us	10	10	100.00
singlebit_err_counter				4	5	80.00
	flash_ctrl_serr_counter	3249.960s	200000.000us	4	5	80.00
singlebit_err_address				3	5	60.00
	flash_ctrl_serr_address	1129.730s	200000.000us	3	5	60.00
scramble				58	62	93.55
	flash_ctrl_wo	3465.500s	200000.000us	19	20	95.00
	flash_ctrl_write_word_sweep	11.550s	44.000us	1	1	100.00
	flash_ctrl_read_word_sweep	10.950s	47.450us	1	1	100.00
	flash_ctrl_ro	119.620s	5887.780us	20	20	100.00
	flash_ctrl_rw	468.040s	4415.456us	17	20	85.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	29.890s	327.474us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	819.190s	160797.184us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	241.440s	10019.418us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	14.340s	54.068us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	13.800s	91.116us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	19.810s	339.270us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	19.810s	339.270us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	42.050s	863.908us	5	5	100.00
	flash_ctrl_csr_rw	18.620s	225.286us	20	20	100.00
	flash_ctrl_csr_aliasing	50.690s	1692.547us	5	5	100.00
	flash_ctrl_same_csr_outstanding	32.370s	63.253us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	42.050s	863.908us	5	5	100.00
	flash_ctrl_csr_rw	18.620s	225.286us	20	20	100.00
	flash_ctrl_csr_aliasing	50.690s	1692.547us	5	5	100.00
	flash_ctrl_same_csr_outstanding	32.370s	63.253us	20	20	100.00

V2S

478/485 passed

98.56 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	66.310s	156.379us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	66.310s	156.379us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	66.310s	156.379us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	66.310s	156.379us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	89.840s	273.297us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_sec_cm	2379.220s	3449.018us	5	5	100.00
	flash_ctrl_tl_intg_err	567.780s	850.796us	20	20	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	567.780s	850.796us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	567.780s	850.796us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	29.430s	233.764us	3	3	100.00
	flash_ctrl_wr_intg	13.120s	191.152us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	160.940s	68.629us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	135.350s	39.178us	80	80	100.00
	flash_ctrl_disable	22.920s	143.610us	50	50	100.00
	flash_ctrl_sec_info_access	75.750s	1961.536us	50	50	100.00
	flash_ctrl_connect	17.240s	32.958us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	13.240s	113.905us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.620s	225.286us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	66.310s	156.379us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.620s	225.286us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	66.310s	156.379us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.620s	225.286us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	66.310s	156.379us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	22.920s	143.610us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	29.430s	233.764us	3	3	100.00
	flash_ctrl_access_after_disable	13.170s	64.779us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	26.920s	27.708us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	22.920s	143.610us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	30.290s	7143.352us	10	10	100.00
sec_cm_mem_scramble				17	20	85.00
	flash_ctrl_rw	468.040s	4415.456us	17	20	85.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	189.820s	2276.239us	10	10	100.00
	flash_ctrl_rw_derr	259.050s	7249.030us	10	10	100.00
	flash_ctrl_integrity	455.930s	3849.959us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1715.420s	135770.142us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2379.220s	3449.018us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2379.220s	3449.018us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2379.220s	3449.018us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2379.220s	3449.018us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	26.070s	802.825us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				3	5	60.00
	flash_ctrl_phy_host_grant_err	14.190s	38.739us	3	5	60.00
sec_cm_phy_ack_ctrl_consistency				3	5	60.00
	flash_ctrl_phy_ack_consistency	12.970s	23.901us	3	5	60.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2379.220s	3449.018us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2379.220s	3449.018us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2379.220s	3449.018us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	26.720s	605.988us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	538.930s	771.938us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job killed!
	flash_ctrl_rw	84681985424639571072064364291359923951064148054653470332924521375807444418671	None
	flash_ctrl_intr_wr_slow_flash	93973735343027593331930306391240691482159596165775942240920944337387728505461	None
	flash_ctrl_serr_address	35342904224018685359268631810934163369352172906863602988428069849364507257852	None
	flash_ctrl_rw	90096711329319967414792939292171847138689588850866901966587179133940976900164	None
	flash_ctrl_intr_wr_slow_flash	49502279668557128661332236882446653359158931386629339352263990551500184781381	None
	flash_ctrl_prog_reset	23180786939809617251343600589792151870719782200957363701772838481229620196344	None
	flash_ctrl_rw	50109551855299017130030006231376587662423857276068931729680890176213913879771	None
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue
	flash_ctrl_serr_counter	93525311351707064098075521601331598373612026996954138206266816770275707230643	108	UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_wo	103483054099251441114647014138350773486753927229519178853139053958528061329651	108	UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_serr_address	6499598281053380554343326845447767331439188704286756083394707540603462375470	108	UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	flash_ctrl_phy_ack_consistency	94380401424271406942983064390064852370033043738978007889056136502176011791227	116	UVM_INFO @ 19016.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_ack_consistency	72408382490693045254790501315564620205776472472521499190586375841828154620419	116	UVM_INFO @ 21283.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:
	flash_ctrl_rw_evict	90415434641153058375634302376526696869753555702622898284802887646659190501189	108	UVM_INFO @ 10631.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	15663547177614391058842880579626516698304005350557510371086561965717412353373	108	UVM_INFO @ 13664.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
	flash_ctrl_phy_host_grant_err	57944753557054210125942469673465190224325112547301011061299222149447816453793	125	UVM_ERROR @ 20184.8 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 20184.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	113896778344197013823814350668240198522196079470047932571565024104067045289242	125	UVM_ERROR @ 38940.7 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 38940.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (* [] vs [*])
	flash_ctrl_error_mp	17408244470588420732154753611147590184421157180120396888474437087023602664464	864	UVM_INFO @ 13221651.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp b103e61_54c3801e:ffffffff_ffffffff mismatch!!
	flash_ctrl_intr_rd	81159152244289559945027019770877413928819359868948705313866248279653816395202	108	UVM_INFO @ 618297.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---