Simulation Results: gpio

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.37 %
  • code
  • 98.27 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 93.94 %
Validation stages
V1
100.00%
V2
92.84%
V2S
100.00%
V3
38.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 200 200 100.00
gpio_smoke 1.750s 73.897us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.930s 238.852us 50 50 100.00
gpio_smoke_en_cdc_prim 1.650s 328.533us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.710s 108.211us 50 50 100.00
csr_hw_reset 5 5 100.00
gpio_csr_hw_reset 0.930s 13.269us 5 5 100.00
csr_rw 20 20 100.00
gpio_csr_rw 0.960s 15.811us 20 20 100.00
csr_bit_bash 5 5 100.00
gpio_csr_bit_bash 2.560s 275.925us 5 5 100.00
csr_aliasing 5 5 100.00
gpio_csr_aliasing 1.310s 116.673us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
gpio_csr_mem_rw_with_rand_reset 1.620s 45.163us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
gpio_csr_rw 0.960s 15.811us 20 20 100.00
gpio_csr_aliasing 1.310s 116.673us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 100 100 100.00
gpio_random_dout_din 1.550s 69.532us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.600s 202.204us 50 50 100.00
out_in_regs_read_write 50 50 100.00
gpio_dout_din_regs_random_rw 1.310s 202.917us 50 50 100.00
gpio_interrupt_programming 50 50 100.00
gpio_intr_rand_pgm 1.680s 95.525us 50 50 100.00
random_interrupt_trigger 50 50 100.00
gpio_rand_intr_trigger 3.320s 285.299us 50 50 100.00
interrupt_and_noise_filter 50 50 100.00
gpio_intr_with_filter_rand_intr_event 3.660s 152.918us 50 50 100.00
noise_filter_stress 50 50 100.00
gpio_filter_stress 20.190s 537.044us 50 50 100.00
regs_long_reads_and_writes 50 50 100.00
gpio_random_long_reg_writes_reg_reads 6.530s 347.811us 50 50 100.00
full_random 50 50 100.00
gpio_full_random 1.480s 177.303us 50 50 100.00
stress_all 2 50 4.00
gpio_stress_all 115.170s 19791.546us 2 50 4.00
alert_test 50 50 100.00
gpio_alert_test 0.950s 84.302us 50 50 100.00
intr_test 50 50 100.00
gpio_intr_test 0.930s 34.011us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
gpio_tl_errors 2.780s 565.082us 20 20 100.00
tl_d_illegal_access 20 20 100.00
gpio_tl_errors 2.780s 565.082us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
gpio_csr_rw 0.960s 15.811us 20 20 100.00
gpio_same_csr_outstanding 1.200s 64.264us 20 20 100.00
gpio_csr_aliasing 1.310s 116.673us 5 5 100.00
gpio_csr_hw_reset 0.930s 13.269us 5 5 100.00
tl_d_partial_access 50 50 100.00
gpio_csr_rw 0.960s 15.811us 20 20 100.00
gpio_same_csr_outstanding 1.200s 64.264us 20 20 100.00
gpio_csr_aliasing 1.310s 116.673us 5 5 100.00
gpio_csr_hw_reset 0.930s 13.269us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
gpio_tl_intg_err 1.930s 686.048us 20 20 100.00
gpio_sec_cm 1.440s 91.645us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
gpio_tl_intg_err 1.930s 686.048us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 38 50 76.00
gpio_rand_straps 0.940s 17.161us 38 50 76.00
stress_all_with_rand_reset 0 50 0.00
gpio_stress_all_with_rand_reset 18.480s 1772.760us 0 50 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
gpio_stress_all 87365407215676114999301818043178514962341932814919656465761261219134393694270 1821
UVM_INFO @ 30148877497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 106488982449985595654219677265433211718485819602931237091899616963014228672474 75
UVM_INFO @ 7081626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 32216649962570329503968673024667765919994828128524734195332153060525539417826 911
UVM_INFO @ 7479994835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 93749581183018480314175501138350866007191993493462593856829046089147611716302 2199
UVM_INFO @ 24430748233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 48307270022739234516055949588376996754516811132716804594553147182950549544222 291
UVM_INFO @ 7565189831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 12899466151569143707780681464698668582666656554639317615717475620355481172695 1154
UVM_INFO @ 11006498094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 51154668554464255571765435396691588651396780170639655519824223542791347493628 1581
UVM_INFO @ 4298909240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 107400311897675822354679253972044549969508335309762926924294014163076052413318 1081
UVM_INFO @ 4963188618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 79256544176735119930600888094679063650021027831567361017202966605090920767943 130
UVM_INFO @ 2643528824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 93237169627481421971958009605857342128215046188754283588852398954271010961660 75
UVM_INFO @ 3713581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 1293250764815963529499690864480280577523321930017490565259858911976409919452 77
UVM_INFO @ 103972384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 84417709668760971254844993286630805315520196296512042336763123321759720518532 879
UVM_INFO @ 31423968697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 103193021903944196029530423285972918754672178174746345694750519970033495985942 241
UVM_INFO @ 1118507166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 83423457038140871392342129850238192429121647805122298087609831625934290569608 957
UVM_INFO @ 1933860355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 40466491599859781889355338784548828928004523489681926852109774974617399742227 276
UVM_INFO @ 1308000460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 89581833088700790113944505033351117899220166733637123251972215766715560104652 75
UVM_INFO @ 1534274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 40509964203608734974106824267040805893218338400218486029560122318052010262855 3825
UVM_INFO @ 32084907880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 94717760288241569152439264182078487596749075055250852174308968416873712487592 1256
UVM_INFO @ 6311503421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 70516370384155477863575423203370423434371389155189627459426113260926817739364 75
UVM_INFO @ 1539388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 66404468722307723522090309559612645082732882785442495600557175768435569831286 76
UVM_INFO @ 7820275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 68341138203327480507374941223894696972871343463757712765737272942761436395132 75
UVM_INFO @ 3915314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 90955540966729227038513299681692605368331625221532044147511719174187664556353 79
UVM_INFO @ 454567584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 12778203752749703979859067593841466946771247339131540468514370597426856241163 695
UVM_INFO @ 2026175014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 50221791329862896858135190125048406752975725967652911130550121242885482895919 180
UVM_INFO @ 656987274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 83398603158227727121899119735964619655428829917686619388250772640070785920032 199
UVM_INFO @ 1504633373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 22844095362461243120409397718868573941539320813720099714305016441788446815390 75
UVM_INFO @ 3722661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 94767559241234091655871260052163379983723794097971998754865924924882460536224 76
UVM_INFO @ 288117595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 33233783004386977699145377973033305211782870673958780466488320998507409013691 319
UVM_INFO @ 172728009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 82383578893970226471563184980000908712753526688714728663452085888409413271680 1970
UVM_INFO @ 2091357939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 75196093613128893242732737516637812981774885923176598355132224319006412686780 971
UVM_INFO @ 5601435487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 42271454726569904941413161742802379943097014174779362812039208301094616582122 694
UVM_INFO @ 4269367091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 85956653167872084869460822193118952089194281491868229686638261005219912346093 1371
UVM_INFO @ 12215093375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 53748662777060438621392317773859798836835034675719767827297334641726243451055 811
UVM_INFO @ 1505441299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 51405105457398751990410213458836615856090665162081437734404405561281394695508 75
UVM_INFO @ 8335081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 480201516162577426157552556427866370429709263797076097018310609003600014612 213
UVM_INFO @ 882839882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 17675978936195367628349765445398443292634028506481514750731349298187056448848 79
UVM_INFO @ 609429072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 35118322791292235606015635101548083108302251305245163296273348248891890938130 75
UVM_INFO @ 7039956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 1945527096935819515283513752235034945330116525226499109198934990387026123493 1914
UVM_INFO @ 5741353850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 42282126624696266915220572509292606579970666409796477338089623356616080037999 75
UVM_INFO @ 5404688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 96664923710496935973149449044624074270176008626012397446766203302128636157820 354
UVM_INFO @ 1291476631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 78748531969763342776766991489556805368196040612725912569069768214306644798901 376
UVM_INFO @ 8414758151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 12134157152619221213790860323196965755490251375601994284456109652597232863425 77
UVM_INFO @ 46400423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 67652915947689808376911146854405348823700818705581299549657467550659592525571 530
UVM_INFO @ 661178293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 12572590919781168140730030907402967169120575673759502491184424606191008395138 3347
UVM_INFO @ 19791545844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 9092116993379375059788917602966618206262678991016828753697427936248312495837 75
UVM_INFO @ 2568503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 66480696937432977263802463051281595956388983474024318614458504768749952872045 923
UVM_INFO @ 2629579912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 74812804946094305447607983893003542097951866880041068566631084657804490151859 767
UVM_INFO @ 1786326079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 112279494806913125333687630627443203330592765332848376184001695767907113271444 75
UVM_INFO @ 826841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 71356416121924655679955292167649287221716006480832061311953350028829672593025 78
UVM_INFO @ 322320505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 39268734375431649829647756951011272662985066452796526734164684377888936456757 526
UVM_INFO @ 4775544838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 39781266756122019272950767009832726388455456577573436269520846418200704975857 304
UVM_INFO @ 4587784472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 114653477654753067168295894877609286931555843956646599228626775078307621318427 718
UVM_INFO @ 2678730712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 112966197869551990995212930382933669235884237166037663966873161311833912844801 75
UVM_INFO @ 3203868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 108762590404830554975115115901713466348584073606187485017035210476705099551344 1462
UVM_INFO @ 3049750573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 101285755509215800393775032626341581685309885363588027807572832481857879846228 1374
UVM_INFO @ 1625378641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 97103397726721436733868554552222113419454769444002703051389936383360623462608 1971
UVM_INFO @ 3439784226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 35653181992907162323222843032328018718121812994395623726546293867514902929385 1554
UVM_INFO @ 9777801757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 29810075841491674252688097698792731443495145073228826504358263082668216990336 524
UVM_INFO @ 7522341207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 47139574341710970683271688352525595165876154957971388112195167638507510039492 75
UVM_INFO @ 1063151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 30595828176129515270914407959390750291632070882544363547093999202784543647292 1435
UVM_INFO @ 3496457770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done)
gpio_stress_all_with_rand_reset 53534864239069291579887162329891747149757222483974578249606854837668028098489 82
UVM_INFO @ 965296384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 45911108994841526780119308871249965913634259226407213438709014883346333297648 84
UVM_INFO @ 6411999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 17422712429539901984394799463667836073458717496418766460517668373328341261260 80
UVM_INFO @ 51567660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 16535332033804150808791728753966941962578573552663798157747625490080521493959 80
UVM_INFO @ 28052880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 60068736233188028218041352778175200603318830319303909691618112393562967715436 84
UVM_INFO @ 1021557990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 85219828124211857982060844854976484465121919350849019504094783214180238387893 81
UVM_INFO @ 588413039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 83104095630890643988929075611401566139728425289501559733292212967412341569651 80
UVM_INFO @ 118176743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 1542092591183543154957795990820646556780064591291955884652885238413915462583 80
UVM_INFO @ 3700489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 37456160632224590767014312272519074268198709033532428119468283889769727708165 282
UVM_INFO @ 867294797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 376259975391399088970705055624039853899693209231972625770940014727421927904 90
UVM_INFO @ 8913269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 78562425554817821212156948182091131288249820949642239791622184064801480946197 80
UVM_INFO @ 9413848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 4830060912092204796686307670405847062120252755747590485974697304065671093869 85
UVM_INFO @ 569818225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 57266964601599324194861641481458602718348388939672843390076714515916580537330 242
UVM_INFO @ 76221491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 27374570007812574310219855314239464212132590955071130592380744835719936484757 80
UVM_INFO @ 253695037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 115692012583407055034252994499844190524541966762062485390514075722465389853474 83
UVM_INFO @ 1557511702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 24494166068189069753261772018991974080637651184424322424603634040902610846652 672
UVM_INFO @ 1772759987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 54081801537047156878748470369499388389980751118998705186552573753990762293748 80
UVM_INFO @ 7812205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 5788817690828332152076861022156243872612688820567400193354848878647188830798 82
UVM_INFO @ 540125357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 24546185651625926157573729741604890036075172457343605813969844563809627954928 305
UVM_INFO @ 763873980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 81841320723890890872785772175037032840792386316410888569462167089129214157032 298
UVM_INFO @ 1818670180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 86802744785335034054646698346772278610420295513665508414874848979823644233284 82
UVM_INFO @ 400723649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100054206649119169109577589351519327523956934670987141963978273947545525816197 80
UVM_INFO @ 2299462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 52249567986003421293315178914276112830094929247871820678342353521030841559825 80
UVM_INFO @ 3939973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -*
gpio_stress_all_with_rand_reset 108427645449871634222287051432046611080871277161892463154078111896947805980602 81
UVM_INFO @ 1038941946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 85126108980970787747325101877241558853407071897785738978656664162011784241582 78
UVM_INFO @ 4896627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 78466398220219017063391438677315503452133077247298671631398188254961084485341 79
UVM_INFO @ 256292375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58430721476870747528102177009470792017513567411653312271720072200086789153617 78
UVM_INFO @ 1253015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58296702205718993179297144841148393778978388043375117737420958875193352368172 78
UVM_INFO @ 12384174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 87409230516686859446819015864547756380630892225279524639762798926812450070674 78
UVM_INFO @ 115708366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 39296294757354373127957549920272597418574013326174691992374141440069388288447 413
UVM_INFO @ 1925200831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 70689331129539064403264202891863693080764548285427871076239412890597137029603 78
UVM_INFO @ 2658760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 107127022917002948857805223211977730228779070283360310240801395881970482804768 78
UVM_INFO @ 6250290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 22190745454178226471995673698096131010756832803505327547266873299318349746062 220
UVM_INFO @ 1164757813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 38475364488306729610883454678687095967414917311576792085102588854780951886500 394
UVM_INFO @ 589556043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 105121716578203038050182291398989738170602513193649133754868899015135320826454 481
UVM_INFO @ 468262978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 80899834235821259810994397914421604653834727942838010955634937154850713594443 78
UVM_INFO @ 3573185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 6695796953270296571849414448850085513508718213063721742564760470599575853373 79
UVM_INFO @ 935358353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 16100626558193252861731457402618225043231088545566785330524752939170540524295 78
UVM_INFO @ 44582510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 50751021477576092308681272983062050486338483950372547426169788496589313721774 238
UVM_INFO @ 582368627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 83634110335034179959213154453091949459302158054465543226780607767941704320198 78
UVM_INFO @ 5612300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 52010882732142080756285508255563728298926257156256088987118339963791024062446 78
UVM_INFO @ 609583614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 3523122068083488589496649670319744660976341869880762830255480415872405865492 78
UVM_INFO @ 205806907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 12371913824674708834481841180301197581039315892884110447521270510695295246333 79
UVM_INFO @ 130008311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 107671854083411557105374892044410628767677472664051461649762578949137623369658 78
UVM_INFO @ 2492128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100212786813376382517270508445940951273061684872812895314662265321963770300267 80
UVM_INFO @ 717158007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 46475912413257647461317867410597858871371140526400770500691317961172211576728 80
UVM_INFO @ 2168514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 89395924093670474397783337296547874788612189064142188098068994168061589541540 78
UVM_INFO @ 4184996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 57075444306577279729993715041224304454334531528365645527553803225367965510583 79
UVM_INFO @ 1043967991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 89169780442348750150067531771849015646326704125567233109562257126038458240866 78
UVM_INFO @ 8574362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 91271405512981653376741063838008601397555388102270772028132379117685183804129 78
UVM_INFO @ 5849976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---