Simulation Results: hmac

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.04 %
  • code
  • 99.32 %
  • assert
  • 97.80 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 13.910s 2091.438us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.310s 116.887us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.300s 151.796us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 14.630s 333.411us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.900s 161.477us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 1151.870s 391968.893us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.300s 151.796us 20 20 100.00
hmac_csr_aliasing 6.900s 161.477us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 96.550s 51115.705us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 86.650s 1830.614us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 260.810s 7072.903us 30 30 100.00
hmac_test_sha384_vectors 568.740s 14903.719us 75 75 100.00
hmac_test_sha512_vectors 527.510s 110041.784us 75 75 100.00
hmac_test_hmac256_vectors 14.240s 753.574us 50 50 100.00
hmac_test_hmac384_vectors 15.790s 1522.819us 60 60 100.00
hmac_test_hmac512_vectors 17.120s 435.470us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 36.350s 6347.808us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1171.590s 12499.299us 10 10 100.00
error 10 10 100.00
hmac_error 151.510s 12271.759us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 128.730s 7151.030us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 13.910s 2091.438us 10 10 100.00
hmac_long_msg 96.550s 51115.705us 10 10 100.00
hmac_back_pressure 86.650s 1830.614us 25 25 100.00
hmac_datapath_stress 1171.590s 12499.299us 10 10 100.00
hmac_burst_wr 36.350s 6347.808us 50 50 100.00
hmac_stress_all 2082.650s 43597.511us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 13.910s 2091.438us 10 10 100.00
hmac_long_msg 96.550s 51115.705us 10 10 100.00
hmac_back_pressure 86.650s 1830.614us 25 25 100.00
hmac_datapath_stress 1171.590s 12499.299us 10 10 100.00
hmac_wipe_secret 128.730s 7151.030us 10 10 100.00
hmac_test_sha256_vectors 260.810s 7072.903us 30 30 100.00
hmac_test_sha384_vectors 568.740s 14903.719us 75 75 100.00
hmac_test_sha512_vectors 527.510s 110041.784us 75 75 100.00
hmac_test_hmac256_vectors 14.240s 753.574us 50 50 100.00
hmac_test_hmac384_vectors 15.790s 1522.819us 60 60 100.00
hmac_test_hmac512_vectors 17.120s 435.470us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 13.910s 2091.438us 10 10 100.00
hmac_long_msg 96.550s 51115.705us 10 10 100.00
hmac_back_pressure 86.650s 1830.614us 25 25 100.00
hmac_datapath_stress 1171.590s 12499.299us 10 10 100.00
hmac_burst_wr 36.350s 6347.808us 50 50 100.00
hmac_error 151.510s 12271.759us 10 10 100.00
hmac_wipe_secret 128.730s 7151.030us 10 10 100.00
hmac_test_sha256_vectors 260.810s 7072.903us 30 30 100.00
hmac_test_sha384_vectors 568.740s 14903.719us 75 75 100.00
hmac_test_sha512_vectors 527.510s 110041.784us 75 75 100.00
hmac_test_hmac256_vectors 14.240s 753.574us 50 50 100.00
hmac_test_hmac384_vectors 15.790s 1522.819us 60 60 100.00
hmac_test_hmac512_vectors 17.120s 435.470us 75 75 100.00
hmac_stress_all 2082.650s 43597.511us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2082.650s 43597.511us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.920s 101.908us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.960s 23.506us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.660s 268.701us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.660s 268.701us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.310s 116.887us 5 5 100.00
hmac_csr_rw 1.300s 151.796us 20 20 100.00
hmac_csr_aliasing 6.900s 161.477us 5 5 100.00
hmac_same_csr_outstanding 2.880s 149.089us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.310s 116.887us 5 5 100.00
hmac_csr_rw 1.300s 151.796us 20 20 100.00
hmac_csr_aliasing 6.900s 161.477us 5 5 100.00
hmac_same_csr_outstanding 2.880s 149.089us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.380s 253.444us 5 5 100.00
hmac_tl_intg_err 4.790s 267.272us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.790s 267.272us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 13.910s 2091.438us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.270s 114.088us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 789.910s 33774.160us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.870s 62.667us 1 1 100.00