Simulation Results

Simulation Results: keymgr

12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.92 %

code
98.99 %

assert
97.72 %

func
91.06 %

line
99.20 %

branch
99.00 %

cond
97.84 %

toggle
98.89 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.35%
V2S		99.48%
V3		56.00%

155/155 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	keymgr_smoke	43.500s	6424.074us	50	50	100.00
random				50	50	100.00
	keymgr_random	28.430s	5643.719us	50	50	100.00
csr_hw_reset				5	5	100.00
	keymgr_csr_hw_reset	1.630s	105.790us	5	5	100.00
csr_rw				20	20	100.00
	keymgr_csr_rw	1.570s	52.468us	20	20	100.00
csr_bit_bash				5	5	100.00
	keymgr_csr_bit_bash	15.380s	2608.689us	5	5	100.00
csr_aliasing				5	5	100.00
	keymgr_csr_aliasing	11.440s	361.615us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	keymgr_csr_mem_rw_with_rand_reset	2.590s	114.141us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	keymgr_csr_rw	1.570s	52.468us	20	20	100.00
	keymgr_csr_aliasing	11.440s	361.615us	5	5	100.00

765/770 passed

99.35 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
cfgen_during_op				50	50	100.00
	keymgr_cfg_regwen	87.610s	2341.899us	50	50	100.00
sideload				199	200	99.50
	keymgr_sideload	21.740s	3755.853us	50	50	100.00
	keymgr_sideload_kmac	44.680s	1539.003us	50	50	100.00
	keymgr_sideload_aes	32.470s	3843.304us	50	50	100.00
	keymgr_sideload_otbn	40.300s	19285.938us	49	50	98.00
direct_to_disabled_state				50	50	100.00
	keymgr_direct_to_disabled	19.630s	6984.707us	50	50	100.00
lc_disable				49	50	98.00
	keymgr_lc_disable	17.180s	1700.974us	49	50	98.00
kmac_error_response				49	50	98.00
	keymgr_kmac_rsp_err	13.910s	647.860us	49	50	98.00
invalid_sw_input				50	50	100.00
	keymgr_sw_invalid_input	25.570s	1065.678us	50	50	100.00
invalid_hw_input				50	50	100.00
	keymgr_hwsw_invalid_input	42.850s	12607.466us	50	50	100.00
sync_async_fault_cross				50	50	100.00
	keymgr_sync_async_fault_cross	8.120s	1299.123us	50	50	100.00
stress_all				48	50	96.00
	keymgr_stress_all	170.990s	34032.195us	48	50	96.00
intr_test				50	50	100.00
	keymgr_intr_test	1.230s	40.282us	50	50	100.00
alert_test				50	50	100.00
	keymgr_alert_test	1.430s	75.681us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	keymgr_tl_errors	5.760s	124.078us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	keymgr_tl_errors	5.760s	124.078us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	keymgr_csr_hw_reset	1.630s	105.790us	5	5	100.00
	keymgr_csr_rw	1.570s	52.468us	20	20	100.00
	keymgr_csr_aliasing	11.440s	361.615us	5	5	100.00
	keymgr_same_csr_outstanding	5.040s	128.623us	20	20	100.00
tl_d_partial_access				50	50	100.00
	keymgr_csr_hw_reset	1.630s	105.790us	5	5	100.00
	keymgr_csr_rw	1.570s	52.468us	20	20	100.00
	keymgr_csr_aliasing	11.440s	361.615us	5	5	100.00
	keymgr_same_csr_outstanding	5.040s	128.623us	20	20	100.00

V2S

383/385 passed

99.48 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
tl_intg_err				25	25	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
	keymgr_tl_intg_err	7.640s	1220.836us	20	20	100.00
shadow_reg_update_error				20	20	100.00
	keymgr_shadow_reg_errors	5.580s	751.989us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	keymgr_shadow_reg_errors	5.580s	751.989us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	keymgr_shadow_reg_errors	5.580s	751.989us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	keymgr_shadow_reg_errors	5.580s	751.989us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	keymgr_shadow_reg_errors_with_csr_rw	18.470s	2127.325us	20	20	100.00
prim_count_check				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
prim_fsm_check				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	keymgr_tl_intg_err	7.640s	1220.836us	20	20	100.00
sec_cm_config_shadow				20	20	100.00
	keymgr_shadow_reg_errors	5.580s	751.989us	20	20	100.00
sec_cm_op_config_regwen				50	50	100.00
	keymgr_cfg_regwen	87.610s	2341.899us	50	50	100.00
sec_cm_reseed_config_regwen				70	70	100.00
	keymgr_random	28.430s	5643.719us	50	50	100.00
	keymgr_csr_rw	1.570s	52.468us	20	20	100.00
sec_cm_sw_binding_config_regwen				70	70	100.00
	keymgr_random	28.430s	5643.719us	50	50	100.00
	keymgr_csr_rw	1.570s	52.468us	20	20	100.00
sec_cm_max_key_ver_config_regwen				70	70	100.00
	keymgr_random	28.430s	5643.719us	50	50	100.00
	keymgr_csr_rw	1.570s	52.468us	20	20	100.00
sec_cm_lc_ctrl_intersig_mubi				49	50	98.00
	keymgr_lc_disable	17.180s	1700.974us	49	50	98.00
sec_cm_constants_consistency				50	50	100.00
	keymgr_hwsw_invalid_input	42.850s	12607.466us	50	50	100.00
sec_cm_intersig_consistency				50	50	100.00
	keymgr_hwsw_invalid_input	42.850s	12607.466us	50	50	100.00
sec_cm_hw_key_sw_noaccess				50	50	100.00
	keymgr_random	28.430s	5643.719us	50	50	100.00
sec_cm_output_keys_ctrl_redun				50	50	100.00
	keymgr_sideload_protect	23.280s	1099.030us	50	50	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
sec_cm_data_fsm_sparse				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
sec_cm_ctrl_fsm_local_esc				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
sec_cm_ctrl_fsm_consistency				49	50	98.00
	keymgr_custom_cm	38.250s	4343.680us	49	50	98.00
sec_cm_ctrl_fsm_global_esc				49	50	98.00
	keymgr_lc_disable	17.180s	1700.974us	49	50	98.00
sec_cm_ctrl_ctr_redun				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
sec_cm_kmac_if_fsm_sparse				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
sec_cm_kmac_if_ctr_redun				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
sec_cm_kmac_if_cmd_ctrl_consistency				49	50	98.00
	keymgr_custom_cm	38.250s	4343.680us	49	50	98.00
sec_cm_kmac_if_done_ctrl_consistency				49	50	98.00
	keymgr_custom_cm	38.250s	4343.680us	49	50	98.00
sec_cm_reseed_ctr_redun				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
sec_cm_side_load_sel_ctrl_consistency				49	50	98.00
	keymgr_custom_cm	38.250s	4343.680us	49	50	98.00
sec_cm_sideload_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	21.970s	1367.287us	5	5	100.00
sec_cm_ctrl_key_integrity				49	50	98.00
	keymgr_custom_cm	38.250s	4343.680us	49	50	98.00

28/50 passed

56.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				28	50	56.00
	keymgr_stress_all_with_rand_reset	21.780s	1171.829us	28	50	56.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	keymgr_stress_all_with_rand_reset	77296033569580401869813044833882823831146624806225517212268512439725086583407	1354	UVM_INFO @ 1249563068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	37373516786485054430289495397759787683980175490336083720111032672832289795200	305	UVM_INFO @ 368895798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	89607809292453664484849059686356558030820449319948532117592766581449669479748	459	UVM_INFO @ 182039024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	23864060034341032461366588300284306809787192243332595804985882365726290171385	145	UVM_INFO @ 215040401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	915550576871050937415673003241271319216105169353847236432373072861172026049	209	UVM_INFO @ 108568220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	28317232337315700635351047122689192933477441649032618249551123048886191037587	763	UVM_INFO @ 196521482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	7136865280635980610142831859284711815911208858481290767254127538217921232337	106	UVM_INFO @ 107600821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	89526011281987637497023618149892740427716723241243079879761087560792789559306	422	UVM_INFO @ 639579571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	16873344676355560689798080416350119187594586253678357192275345522095387278866	447	UVM_INFO @ 460252628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	50812703756861217271203506661526479837304839599798474621661022209851158267054	223	UVM_INFO @ 816628908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	112231557003858259085290434078795092250728589292827697866665699548687245964879	927	UVM_INFO @ 411756253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	77981036150388660265034012640499479861099221433291277961769462533682538405963	188	UVM_INFO @ 113557132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	76546301846671727947283808744979046385701067237249661267902311950358842757609	1157	UVM_INFO @ 252081165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	40038460585130205099970501501091840265006271848629568176175623374067092246194	735	UVM_INFO @ 337019967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	38052390604477665677699036335851725088516143651973099087778917479727720108525	444	UVM_INFO @ 486059864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	47231783743512141228598869344796716848093896476378642037033754809634360966905	152	UVM_INFO @ 476345190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	108261147066795129429831123392310073752867516177523254270671697369837616543955	1981	UVM_INFO @ 3233208660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	110092079921308347329402959696250281498502592893872291820417498032867985234268	440	UVM_INFO @ 316852326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	101699201885741536668643476967577716192220978525634413878885572854100122849366	647	UVM_INFO @ 533729678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	65529179836482909179589512654516881632198153034142306256440370990338529379127	102	UVM_INFO @ 178789648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	73169471489780986942859418338240389718921207235974625707710155208449274933265	1712	UVM_INFO @ 3672920793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	70191708071909153084744466793895770667124777379340193985445654079352585774995	512	UVM_INFO @ 633849730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [] vs []) reg name: keymgr_reg_block.sw_share0_output_
	keymgr_stress_all	27634326397230784841311469880188438993293491889650392838503619670759168644597	1217	UVM_INFO @ 881459629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_lc_disable	60914521321034062212543222735858253886799456572231183374578735233642782206468	320	UVM_INFO @ 226131560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_operation_err triggered unexpectedly
	keymgr_kmac_rsp_err	102285846344873067956888248564672133112594435507940550506178946993303264248217	265	UVM_INFO @ 22038313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [] vs []) reg name: keymgr_reg_block.sw_share1_output_
	keymgr_stress_all	7595373122351857592797676582010058016804566730590930066831448343967971633672	252	UVM_INFO @ 71772780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [keymgr_custom_cm_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_fault_err does not trigger!
	keymgr_custom_cm	66432087722342826270539274674338591193361821167495291753536219524143134657348	391	UVM_INFO @ 68082844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
	keymgr_sideload_otbn	33733523041888967605939294429963295089409283883395862809745497500616893851024	90	UVM_INFO @ 6193387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---