Simulation Results: kmac/masked

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.73 %
  • code
  • 94.22 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.18 %
  • branch
  • 97.01 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 80.28 %
Validation stages
V1
100.00%
V2
99.61%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 98.110s 11010.256us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.580s 103.302us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.590s 38.612us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 27.540s 5988.092us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 9.820s 1591.607us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.300s 91.393us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.590s 38.612us 20 20 100.00
kmac_csr_aliasing 9.820s 1591.607us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.110s 16.309us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.890s 41.723us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3882.960s 517303.790us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1296.360s 113514.947us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2056.030s 198635.947us 5 5 100.00
kmac_test_vectors_sha3_256 2170.590s 303992.557us 5 5 100.00
kmac_test_vectors_sha3_384 26.730s 1582.860us 5 5 100.00
kmac_test_vectors_sha3_512 1212.170s 191753.514us 5 5 100.00
kmac_test_vectors_shake_128 3317.330s 2166379.074us 5 5 100.00
kmac_test_vectors_shake_256 371.880s 20977.482us 5 5 100.00
kmac_test_vectors_kmac 3.870s 863.875us 5 5 100.00
kmac_test_vectors_kmac_xof 4.000s 104.255us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 456.520s 35678.313us 50 50 100.00
app 50 50 100.00
kmac_app 337.940s 31539.197us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 362.860s 20756.314us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 381.560s 7733.701us 50 50 100.00
error 50 50 100.00
kmac_error 454.100s 16937.563us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 15.600s 1752.219us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.910s 1949.183us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 46.120s 1354.872us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 38.260s 2323.610us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 68.130s 8213.209us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 34.820s 788.153us 50 50 100.00
stress_all 47 50 94.00
kmac_stress_all 2621.450s 79175.693us 47 50 94.00
intr_test 50 50 100.00
kmac_intr_test 1.230s 31.512us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.400s 57.799us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.560s 644.895us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.560s 644.895us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.580s 103.302us 5 5 100.00
kmac_csr_rw 1.590s 38.612us 20 20 100.00
kmac_csr_aliasing 9.820s 1591.607us 5 5 100.00
kmac_same_csr_outstanding 3.940s 1120.026us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.580s 103.302us 5 5 100.00
kmac_csr_rw 1.590s 38.612us 20 20 100.00
kmac_csr_aliasing 9.820s 1591.607us 5 5 100.00
kmac_same_csr_outstanding 3.940s 1120.026us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.720s 94.860us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.720s 94.860us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.720s 94.860us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.720s 94.860us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.300s 273.234us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 123.960s 9584.776us 5 5 100.00
kmac_tl_intg_err 6.890s 392.728us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 6.890s 392.728us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 34.820s 788.153us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 98.110s 11010.256us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 456.520s 35678.313us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.720s 94.860us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 123.960s 9584.776us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 123.960s 9584.776us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 123.960s 9584.776us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 98.110s 11010.256us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 34.820s 788.153us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 123.960s 9584.776us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 396.600s 49197.008us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 98.110s 11010.256us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 168.150s 3997.341us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 36577397236489967886809969937373814380841685150540944302674401436426166278449 228
UVM_INFO @ 3621466536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_stress_all 38695865939712229405343252135836805418317468664090776376201965264236837265136 204
UVM_INFO @ 18190171815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 6264347782368216531858514285753100029724198036202268526674477637363790927073 80
UVM_INFO @ 48826447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 60078189432213151130054408434661891145603723086138278393724738399435156051638 102
UVM_INFO @ 674733798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---