Simulation Results: kmac/unmasked

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.60 %
  • code
  • 92.37 %
  • assert
  • 97.90 %
  • func
  • 96.54 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.71 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
97.92%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 67.840s 2925.175us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.520s 34.049us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.560s 39.195us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 22.400s 2881.546us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 11.280s 1917.202us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.300s 150.742us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.560s 39.195us 20 20 100.00
kmac_csr_aliasing 11.280s 1917.202us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.060s 13.446us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.920s 173.461us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3269.140s 91885.948us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 795.340s 222635.752us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2036.660s 171440.994us 5 5 100.00
kmac_test_vectors_sha3_256 1934.800s 179852.276us 5 5 100.00
kmac_test_vectors_sha3_384 1364.240s 169256.447us 5 5 100.00
kmac_test_vectors_sha3_512 886.760s 168865.796us 5 5 100.00
kmac_test_vectors_shake_128 2285.010s 103742.984us 5 5 100.00
kmac_test_vectors_shake_256 1716.080s 59498.253us 5 5 100.00
kmac_test_vectors_kmac 2.570s 402.862us 5 5 100.00
kmac_test_vectors_kmac_xof 2.860s 171.505us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 413.590s 20874.555us 50 50 100.00
app 50 50 100.00
kmac_app 290.200s 63058.183us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 265.310s 48098.348us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 311.940s 172933.249us 50 50 100.00
error 49 50 98.00
kmac_error 394.750s 32919.805us 49 50 98.00
key_error 50 50 100.00
kmac_key_error 10.580s 5415.357us 50 50 100.00
sideload_invalid 35 50 70.00
kmac_sideload_invalid 153.750s 10105.702us 35 50 70.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 43.160s 12553.382us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 34.560s 1529.132us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 65.810s 25063.174us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 36.490s 2674.413us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 1915.260s 289421.354us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.160s 17.878us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.200s 46.100us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.780s 319.547us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.780s 319.547us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.520s 34.049us 5 5 100.00
kmac_csr_rw 1.560s 39.195us 20 20 100.00
kmac_csr_aliasing 11.280s 1917.202us 5 5 100.00
kmac_same_csr_outstanding 3.000s 341.477us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.520s 34.049us 5 5 100.00
kmac_csr_rw 1.560s 39.195us 20 20 100.00
kmac_csr_aliasing 11.280s 1917.202us 5 5 100.00
kmac_same_csr_outstanding 3.000s 341.477us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.430s 86.929us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.430s 86.929us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.430s 86.929us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.430s 86.929us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.780s 703.722us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 48.290s 19401.469us 5 5 100.00
kmac_tl_intg_err 6.220s 953.050us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 6.220s 953.050us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 36.490s 2674.413us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 67.840s 2925.175us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 413.590s 20874.555us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.430s 86.929us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 48.290s 19401.469us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 48.290s 19401.469us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 48.290s 19401.469us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 67.840s 2925.175us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 36.490s 2674.413us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 48.290s 19401.469us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 277.990s 50840.582us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 67.840s 2925.175us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 266.950s 35809.924us 7 10 70.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21)
kmac_sideload_invalid 84977011492049089937302237116956741719289035433415918144005845507783331958924 98
UVM_INFO @ 10466565257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 13440979531595692415474769019306389736558728520013286188033445951411308241685 99
UVM_INFO @ 10207984020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 114779573200945350196557793037664894752626385518756824776575443729683047518923 212
UVM_INFO @ 11597569268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 100069427693691067777121578028713152778993788846036674544282479526232989775109 308
UVM_INFO @ 20813257446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=39)
kmac_sideload_invalid 83179092156089675914590950506187456441606281266110942619516156659827422567602 117
UVM_INFO @ 10347594209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 23132302180681370686807450430383085619561847947786498973083429634011719079711 417
UVM_INFO @ 5648130504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)
kmac_sideload_invalid 5415518802562472786092056976673933638355772638775976143700902206875841634452 89
UVM_INFO @ 10087292638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24)
kmac_sideload_invalid 17660233525799017655270684991015473629092868457651136867282398816819439114399 101
UVM_INFO @ 10105701504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 57279375407221239152241199923397003409363106994555905279448303216010679235932 80
UVM_INFO @ 10280481787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 83851498503150417284777194935705396375112189513630301898047696646416003237609 81
UVM_INFO @ 10087248995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 32419142909710271519756408126476767389149723563250238787035167951784904853573 78
UVM_INFO @ 10008787318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 14137797623059751301553236754153961783919516170064903303781578829420507832371 78
UVM_INFO @ 10028527126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 28211550786412997704022990618383778002893813347282864639629256301735608121316 81
UVM_INFO @ 10286112012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 79215860808068695975274106385918914002300910402228411154547768990458138955064 81
UVM_INFO @ 10190713223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 95410653402632336401857574777369635472931383656936384705093569032057083580990 81
UVM_INFO @ 10048300684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_error 18907320772261137356531414393683899684347626123426334190314280298472515448616 205
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 42452262801195244614571217671568091655636107443536399736646234481866042810100 87
UVM_INFO @ 10038500505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 92281075659747329739324679935766935979613127153794422229482536614358775076885 85
UVM_INFO @ 10178194860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19)
kmac_sideload_invalid 40432698960490257000042020803308154534075944107853620302431896565984967071397 96
UVM_INFO @ 10114467727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---