Simulation Results: lc_ctrl/volatile_unlock_disabled

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.18 %
  • code
  • 86.00 %
  • assert
  • 94.27 %
  • func
  • 96.26 %
  • line
  • 97.26 %
  • branch
  • 94.27 %
  • cond
  • 81.64 %
  • toggle
  • 89.54 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
99.32%
V2S
100.00%
V3
42.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 6.940s 359.073us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.510s 17.133us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.580s 19.160us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.250s 621.777us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.710s 497.744us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.240s 35.291us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.580s 19.160us 20 20 100.00
lc_ctrl_csr_aliasing 1.710s 497.744us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 7.680s 118.930us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.570s 378.089us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.270s 71.737us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 5.340s 125.566us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 13.810s 429.939us 50 50 100.00
lc_errors 46 50 92.00
lc_ctrl_errors 12.590s 1516.492us 46 50 92.00
security_escalation 256 260 98.46
lc_ctrl_state_failure 13.810s 429.939us 50 50 100.00
lc_ctrl_prog_failure 5.340s 125.566us 50 50 100.00
lc_ctrl_errors 12.590s 1516.492us 46 50 92.00
lc_ctrl_security_escalation 11.840s 482.118us 50 50 100.00
lc_ctrl_jtag_state_failure 77.600s 3167.486us 20 20 100.00
lc_ctrl_jtag_prog_failure 25.030s 1021.611us 20 20 100.00
lc_ctrl_jtag_errors 88.610s 9423.792us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 18.030s 3519.463us 20 20 100.00
lc_ctrl_jtag_state_post_trans 26.200s 4202.292us 20 20 100.00
lc_ctrl_jtag_prog_failure 25.030s 1021.611us 20 20 100.00
lc_ctrl_jtag_errors 88.610s 9423.792us 20 20 100.00
lc_ctrl_jtag_access 14.880s 817.169us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 32.020s 1448.517us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.840s 2133.398us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.850s 127.508us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 18.420s 4209.118us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 13.500s 2939.553us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.460s 45.460us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.940s 116.646us 10 10 100.00
lc_ctrl_jtag_alert_test 1.870s 255.478us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 20.000s 7068.042us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.510s 71.007us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 374.150s 14711.665us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 2.420s 898.179us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.680s 807.614us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.680s 807.614us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.510s 17.133us 5 5 100.00
lc_ctrl_csr_rw 1.580s 19.160us 20 20 100.00
lc_ctrl_csr_aliasing 1.710s 497.744us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.170s 147.586us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.510s 17.133us 5 5 100.00
lc_ctrl_csr_rw 1.580s 19.160us 20 20 100.00
lc_ctrl_csr_aliasing 1.710s 497.744us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.170s 147.586us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 9.330s 320.470us 5 5 100.00
lc_ctrl_tl_intg_err 4.420s 189.665us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.420s 189.665us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.570s 378.089us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 13.810s 429.939us 50 50 100.00
lc_ctrl_sec_cm 9.330s 320.470us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 13.810s 429.939us 50 50 100.00
lc_ctrl_sec_cm 9.330s 320.470us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 13.810s 429.939us 50 50 100.00
lc_ctrl_sec_cm 9.330s 320.470us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 13.810s 429.939us 50 50 100.00
lc_ctrl_sec_cm 9.330s 320.470us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 13.810s 429.939us 50 50 100.00
lc_ctrl_sec_cm 9.330s 320.470us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 13.810s 429.939us 50 50 100.00
lc_ctrl_sec_cm 9.330s 320.470us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 13.810s 429.939us 50 50 100.00
lc_ctrl_sec_cm 9.330s 320.470us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 13.810s 429.939us 50 50 100.00
lc_ctrl_sec_cm 9.330s 320.470us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 11.840s 482.118us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 7.680s 118.930us 50 50 100.00
lc_ctrl_jtag_state_post_trans 26.200s 4202.292us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 18.720s 6832.499us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 18.720s 6832.499us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 18.750s 821.342us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 14.930s 1886.249us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 14.930s 1886.249us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 21 50 42.00
lc_ctrl_stress_all_with_rand_reset 150.090s 20628.998us 21 50 42.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 27738639045478094440576645503392399410352710964535265554480177798260868420216 5993
UVM_INFO @ 10945842947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 40528661842429528128117066687522718905993805458487770749940048605324362799276 1476
UVM_INFO @ 598806388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20539043960608768264478174980389347537348379926064928455610257961631158089891 152
UVM_INFO @ 324182890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 31608819879240167515771806587369090418454648089404945360232906407878344760530 1672
UVM_INFO @ 2676114105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108261113077859884269326685019747291021404491119492327844099601755814744232460 228
UVM_INFO @ 1293867841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51659605398041633412481149303678906543523537519955626356522528845330556806359 12156
UVM_INFO @ 42351980568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 94306722259635036959064867534863914959589111005173186584307223668909686200630 1064
UVM_INFO @ 3614055589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96819118431495226064023870635143974794214162205508023323197302647416461663253 4327
UVM_INFO @ 2631020974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 114555094857318715633993361647740863562437756239019903753828489475653524783851 5749
UVM_INFO @ 4996582106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 8660220644508317659305521897226523657274496228570138600659106162423461760514 6446
UVM_INFO @ 1243282363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68507915776223306611811129270142664649030310527455220613896979836171409427750 6333
UVM_INFO @ 1995964098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 12302240097768960074304940015520178976505242364529367734668729729546620902564 206
UVM_INFO @ 1361220956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53342225362867452338041686161522243559709991096442178169527519476553751612571 150
UVM_INFO @ 110347794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 97113725402838111927285042642577854182914662562553300032083874065639564773171 150
UVM_INFO @ 209653460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60566179914934528679996273847002550882660529020746587787433801567835323590048 1575
UVM_INFO @ 1026845925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 54160219605754911462670848574856196289385128406366453516525754103062029818577 6240
UVM_INFO @ 11080221991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 52211138176491831257630084326816443950400933460446456868505082242087366707251 370
UVM_INFO @ 419448886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 52125154834585398295187958377612203464485471372474777746650595404377268214130 1662
UVM_INFO @ 2513274637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 2183531179660117395292255985235346835566985640204532839107301857725544062918 298
UVM_INFO @ 121800051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 58091831092361067923158034293623656888407035434318784386570108937794351754949 5622
UVM_INFO @ 3388426219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 79330268614191335618267002522071933779466245315240273186705540391483721971570 3898
UVM_INFO @ 3261556823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 62941186873793652663674915386899121008033745291558511611213918045706590471063 223
UVM_INFO @ 5993122086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 17116710828175249803139727677864930454527140573779987130200124140788702768127 260
UVM_INFO @ 709706331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96656502948738695030825370853561122410295799010930732569994949830553242227540 4427
UVM_INFO @ 2673265883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 8576829400149098612275561460688141039143864793605253588396882750684826824697 1135
UVM_INFO @ 7389480925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 86200411489292507131357149673687274982113462952032023452830033794053219910734 8409
UVM_INFO @ 4607843075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 64690755384701273765562005808276430986593206688008788229585606551325707105757 1618
UVM_INFO @ 4413664866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 60879853102860020348460781997117067300242892542435267690264501364443196081014 1677
UVM_INFO @ 278857301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30776025308503182534352455785651189032169666079196704326338129368673712779391 4556
UVM_INFO @ 1983706973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 59891884457480943946112192903554649905401630554787568678302186041109066602901 487
UVM_INFO @ 36146977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 27873810400067504258516998512505153414073535489106897880769779692343060867522 581
UVM_INFO @ 29248362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 34549955847372565428810728568817609600692887997967466103035792189706702530472 626
UVM_INFO @ 47004974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
lc_ctrl_stress_all_with_rand_reset 92108206004973231089221290146916609292805449647403638606296602214568285834753 None
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked*
lc_ctrl_stress_all_with_rand_reset 62226605410164805323987262488429835289296605432148100981283381363196885527567 6594
UVM_INFO @ 5886155913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---