Simulation Results: lc_ctrl/volatile_unlock_enabled

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.25 %
  • code
  • 86.24 %
  • assert
  • 94.41 %
  • func
  • 96.09 %
  • line
  • 97.24 %
  • branch
  • 94.36 %
  • cond
  • 81.84 %
  • toggle
  • 89.54 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.04%
V2S
100.00%
V3
44.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 6.450s 860.866us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.190s 44.627us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.330s 15.919us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.110s 251.896us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.530s 36.330us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.270s 29.882us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.330s 15.919us 20 20 100.00
lc_ctrl_csr_aliasing 1.530s 36.330us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.130s 375.361us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.890s 1477.387us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.220s 14.033us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.520s 635.098us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 11.960s 720.838us 50 50 100.00
lc_errors 45 50 90.00
lc_ctrl_errors 13.520s 921.473us 45 50 90.00
security_escalation 254 260 97.69
lc_ctrl_state_failure 11.960s 720.838us 50 50 100.00
lc_ctrl_prog_failure 4.520s 635.098us 50 50 100.00
lc_ctrl_errors 13.520s 921.473us 45 50 90.00
lc_ctrl_security_escalation 12.450s 603.159us 50 50 100.00
lc_ctrl_jtag_state_failure 55.640s 2643.056us 20 20 100.00
lc_ctrl_jtag_prog_failure 17.040s 785.745us 20 20 100.00
lc_ctrl_jtag_errors 91.800s 19256.736us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 10.320s 2012.558us 20 20 100.00
lc_ctrl_jtag_state_post_trans 19.270s 732.967us 20 20 100.00
lc_ctrl_jtag_prog_failure 17.040s 785.745us 20 20 100.00
lc_ctrl_jtag_errors 91.800s 19256.736us 19 20 95.00
lc_ctrl_jtag_access 12.820s 681.729us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 23.660s 5458.285us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.790s 239.499us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.610s 148.151us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 20.380s 1448.108us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 16.130s 3680.133us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.670s 73.632us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.840s 517.534us 10 10 100.00
lc_ctrl_jtag_alert_test 2.650s 206.605us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 20.070s 1149.441us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.630s 26.925us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 414.670s 56129.327us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.880s 40.027us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.740s 237.338us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.740s 237.338us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.190s 44.627us 5 5 100.00
lc_ctrl_csr_rw 1.330s 15.919us 20 20 100.00
lc_ctrl_csr_aliasing 1.530s 36.330us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.880s 158.979us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.190s 44.627us 5 5 100.00
lc_ctrl_csr_rw 1.330s 15.919us 20 20 100.00
lc_ctrl_csr_aliasing 1.530s 36.330us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.880s 158.979us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 9.650s 2191.381us 5 5 100.00
lc_ctrl_tl_intg_err 3.260s 440.911us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.260s 440.911us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.890s 1477.387us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 11.960s 720.838us 50 50 100.00
lc_ctrl_sec_cm 9.650s 2191.381us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 11.960s 720.838us 50 50 100.00
lc_ctrl_sec_cm 9.650s 2191.381us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 11.960s 720.838us 50 50 100.00
lc_ctrl_sec_cm 9.650s 2191.381us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 11.960s 720.838us 50 50 100.00
lc_ctrl_sec_cm 9.650s 2191.381us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 11.960s 720.838us 50 50 100.00
lc_ctrl_sec_cm 9.650s 2191.381us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 11.960s 720.838us 50 50 100.00
lc_ctrl_sec_cm 9.650s 2191.381us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 11.960s 720.838us 50 50 100.00
lc_ctrl_sec_cm 9.650s 2191.381us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 11.960s 720.838us 50 50 100.00
lc_ctrl_sec_cm 9.650s 2191.381us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 12.450s 603.159us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.130s 375.361us 50 50 100.00
lc_ctrl_jtag_state_post_trans 19.270s 732.967us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 12.410s 552.139us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 12.410s 552.139us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 11.950s 965.443us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 14.400s 1256.581us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 14.400s 1256.581us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 22 50 44.00
lc_ctrl_stress_all_with_rand_reset 126.710s 5783.399us 22 50 44.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 64711711308895635751577752859646169368849037092296918559995319409746286459208 1915
UVM_INFO @ 3166842096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 74114204953349491113066060560244351982433125561360704607098673978354446945495 11412
UVM_INFO @ 5944128399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24345813341010964899324455859202546421603659816089335976524630127295067173369 2726
UVM_INFO @ 4604492426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29184453999331922727574411599044081077612494057543885338175941841068503448533 10557
UVM_INFO @ 2786898696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53943349234467393695299881335872254186600507368022388595136371180306201799354 3636
UVM_INFO @ 2717047871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 100395364538083496881495893253232643332115680200789730927480409018080346768688 1008
UVM_INFO @ 7126489322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 113981764244319658230724543852147091421757709316090963449573249683163059676998 154
UVM_INFO @ 1116878264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91009439651789402468418230235291805559391213021365302063018460569327460618754 205
UVM_INFO @ 1053612750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 5769600806066296740658972672338540113200913260485896488828240818686452860737 151
UVM_INFO @ 105855589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61984014626103836161378194496130836331744942950860410568424487287854834373965 512
UVM_INFO @ 1136091620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 89332438142919390983750369247000866057997111300856345803139003910415049280339 1446
UVM_INFO @ 1235017314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 72001113981164479954678314225741470416160617674529928361054124545677132909086 787
UVM_INFO @ 1017198918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 110626134253226344102663941114207704932891745061351801954472604302911522212632 312
UVM_INFO @ 1096992748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65388672266722791611973651438607929745118476143617101550930582228810691857395 153
UVM_INFO @ 621385991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27202261890069127912382945112498717817168754303911589464956317358526037863315 7558
UVM_INFO @ 20987058773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108104265574749916755119879332263349729871714850760754983674209244976690561321 714
UVM_INFO @ 1092559190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 54483499286871345351476376591806281071207396108357738553563678165670554967275 5192
UVM_INFO @ 1423319491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91446712119634687030445585935051253886268623702863155071835312381762578790758 5779
UVM_INFO @ 6767858563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 53623696797788547666735341292754446211230306485791787353397588858505634235459 941
UVM_INFO @ 2046733837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92802933889677901051123495987327078288930605035854068456204387234329478997164 5945
UVM_INFO @ 26949574909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 3560270590713796920933672186451594007756576550897515264319070929964232496195 5935
UVM_INFO @ 2907859571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90262454581018042961276318688390254660465704467721538144794257891299426143011 344
UVM_INFO @ 780764316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15585458305074646792504701912956043354814231811584354033623681232891510152620 346
UVM_INFO @ 1373708532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 74782479445966121618312151619768154950582898437007194172194409738145006907128 5564
UVM_INFO @ 13445780278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19759865529578191704056609659134450597084233216958255695660773712568166574926 4717
UVM_INFO @ 972480936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 114764121501546083060633572278461374892590518531798149332540929164016467741345 9140
UVM_INFO @ 10000610644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_errors 62500460463598732060131490440571236556452231379481867380474655850652142791844 1894
UVM_INFO @ 208623761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 81581614566163377595531407404174090043728397800752180337868229115579885478481 5518
UVM_INFO @ 10702052913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 78549528457128674332475228754282844711534537699017756589967529845157704335607 4099
UVM_INFO @ 6575080232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 72740259937421842710880180190924035245311882441261239505858417336822247178045 923
UVM_INFO @ 1756208603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 49393166618134830092099990691447324527578096739946396042168518760421408759898 1297
UVM_INFO @ 951324353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 13465714655092306981085073915476066194097413672752573691739737789802290981870 2225
UVM_INFO @ 426353373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 31885060665334493131327720263235009185900535980140407381792155501009954803931 393
UVM_INFO @ 23530050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 61223708490300035479399905697136326799550009508622352232117390556558080830767 720
UVM_INFO @ 62722923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 22705707767000916146024305551309071096976221846485007340430623762768964427119 2208
UVM_INFO @ 30458713855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---