Simulation Results: otbn

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.97 %
  • code
  • 96.74 %
  • assert
  • 97.16 %
  • func
  • 100.00 %
  • block
  • 99.51 %
  • line
  • 99.66 %
  • branch
  • 93.75 %
  • toggle
  • 93.54 %
  • FSM
  • 100.00 %
Validation stages
V1
99.40%
V2
98.91%
V2S
97.94%
V3
30.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 35.000s 135.636us 1 1 100.00
single_binary 99 100 99.00
otbn_single 30.000s 16.871us 99 100 99.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 31.000s 18.581us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 30.000s 74.453us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 32.000s 99.248us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 31.000s 58.624us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 33.000s 92.702us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 30.000s 74.453us 20 20 100.00
otbn_csr_aliasing 31.000s 58.624us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 149.000s 14001.679us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 51.000s 193.995us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 49.000s 100.277us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 59.000s 2222.762us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 216.000s 875.754us 9 10 90.00
stress_all 10 10 100.00
otbn_stress_all 167.000s 511.022us 10 10 100.00
lc_escalation 58 60 96.67
otbn_escalate 52.000s 156.320us 58 60 96.67
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 31.000s 26.577us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 38.000s 46.362us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 32.000s 54.446us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 30.000s 48.848us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 31.000s 56.153us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 31.000s 56.153us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 31.000s 18.581us 5 5 100.00
otbn_csr_rw 30.000s 74.453us 20 20 100.00
otbn_csr_aliasing 31.000s 58.624us 5 5 100.00
otbn_same_csr_outstanding 31.000s 78.186us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 31.000s 18.581us 5 5 100.00
otbn_csr_rw 30.000s 74.453us 20 20 100.00
otbn_csr_aliasing 31.000s 58.624us 5 5 100.00
otbn_same_csr_outstanding 31.000s 78.186us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 30.000s 54.413us 10 10 100.00
otbn_dmem_err 30.000s 138.830us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 33.000s 29.986us 5 5 100.00
otbn_controller_ispr_rdata_err 39.000s 62.730us 5 5 100.00
otbn_mac_bignum_acc_err 27.000s 57.548us 5 5 100.00
otbn_urnd_err 27.000s 30.924us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 26.000s 63.933us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 31.000s 31.989us 2 2 100.00
otbn_non_sec_partial_wipe 8 10 80.00
otbn_partial_wipe 28.000s 59.243us 8 10 80.00
tl_intg_err 25 25 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
otbn_tl_intg_err 46.000s 508.927us 20 20 100.00
passthru_mem_tl_intg_err 19 20 95.00
otbn_passthru_mem_tl_intg_err 56.000s 236.862us 19 20 95.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 35.000s 135.636us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 30.000s 138.830us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 30.000s 54.413us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 46.000s 508.927us 20 20 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 52.000s 156.320us 58 60 96.67
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 30.000s 54.413us 10 10 100.00
otbn_dmem_err 30.000s 138.830us 15 15 100.00
otbn_zero_state_err_urnd 31.000s 26.577us 5 5 100.00
otbn_illegal_mem_acc 26.000s 63.933us 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 30.000s 16.871us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 30.000s 54.413us 10 10 100.00
otbn_dmem_err 30.000s 138.830us 15 15 100.00
otbn_zero_state_err_urnd 31.000s 26.577us 5 5 100.00
otbn_illegal_mem_acc 26.000s 63.933us 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 52.000s 156.320us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 30.000s 54.413us 10 10 100.00
otbn_dmem_err 30.000s 138.830us 15 15 100.00
otbn_zero_state_err_urnd 31.000s 26.577us 5 5 100.00
otbn_illegal_mem_acc 26.000s 63.933us 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 30.000s 16.871us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 29.000s 51.883us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 30.000s 84.574us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 70.000s 462.253us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 70.000s 462.253us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 34.000s 95.571us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 31.000s 55.532us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 29.000s 45.431us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 29.000s 45.431us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 28.000s 26.598us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 30.000s 16.871us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 30.000s 16.871us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 30.000s 16.871us 99 100 99.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 216.000s 875.754us 9 10 90.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 30.000s 16.871us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 30.000s 16.871us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 36.000s 85.730us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 30.000s 16.871us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 929.000s 5091.085us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
otbn_stress_all_with_rand_reset 644.000s 3987.285us 3 10 30.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 32.000s 87.235us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 27773487462823699653755912923965957058217541391263252408750641840769666132586 167
UVM_INFO @ 232579778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 21462170852115945624921007014770562466901176962780820682864871363773109640586 207
UVM_INFO @ 628046809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 14645292995407372472451110659466913220349957149784734626718132748164061997415 172
UVM_INFO @ 918186568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 61144743039914096709070705461180621995517612591786256167950667569676171671404 172
UVM_INFO @ 3365798675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 5902410261989588255540882739794481171336731391242408699958399647781697847321 292
UVM_INFO @ 752964076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 13354241850610792850263520409056806500863754808308888620548543101064229663575 252
UVM_INFO @ 1009590205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 51209747276683321854301169533224751278396268272518695886549430626113164642818 558
UVM_INFO @ 2365582366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,152): Assertion NoModelErrs has failed
otbn_multi 91501227815302196267048847466451346086313169598802179586160734856666493870454 186
UVM_ERROR @ 633351214 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 633351214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 100832718484358974866889689223995135546659214782508383257932257943487899264456 115
UVM_ERROR @ 40884899 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 40884899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_partial_wipe 8727533247346279751927987293984742687810425242188676564019395264137322990711 115
UVM_INFO @ 8194851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed
otbn_partial_wipe 89867242130017514776233725474974972580588181186573052537262627175493999945876 110
UVM_ERROR @ 32968849 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 32968849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 22201187528404396302071888256006528661539722790228919729195324188414956068486 86
UVM_INFO @ 8102467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_escalate 95466601899539264500674290922871199368974318065390499953974454815252376849265 116
UVM_ERROR @ 49106559 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 49106559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
otbn_single 95337782633234768519580099541029477310540427659456464900790387807771355108495 106
UVM_INFO @ 28810845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---